AHDL register initialisation is NOT stable

[Altera_Forum]

Hi, 

i have a Project using Blocks written in AHDL. Inside, there are signals that MUST be zero on initialization or the whole Device will fail. Referring to e.g. http://cubiccyclonium.org/support/kdb/solutions/1028.html , there is no DEFAULT section for the nodes, hence all registers should be '0'. But this is noch stable. I have measurements proofing that nearly every 100th bootup, one of the regs in the 18k-design is not zero!.  Why is the init bootup value unstable? And what is the Solution?  - Defining DEFAULTS in AHDL? - is there a real difference to hardware/bootup? - Rewriting to VHDL? - Never had such problems under VHDL yet, or didnt see it (when defining defaults to signals and vars) - Is there a config Button in Quartus Studio leading to save register initialization? - Or do i realy have to rewrite all (historic) software blocks to a clean (async) reset system including an hardware redesign routing a reset pin?  Hardware: Cyclon II 35k, Quartus Studio 13.1, init by EPCS16, defined V Core and V IO ramps.  Thank you

[Altera_Forum]

Seeing random failure of power-on reset values suggests a problem with asynchronous release of the reset. The fact that the reset values mostly work clarifies that the POR values are correct. In so far, the problem has nothing to do with AHDL or specifying initial values.  

 I presume that the design parts that are succeptible to asynchronous reset relaese can be identified in a code review, it shouldn't be necessary to rewrite the whole design. Typically all registers that can change it's state on the first clock edge after reset can be affected, e.g. a counter or a state machine that advances from reset to idle state.   I understand that you don't have a reset pin, but a counter based internal self-reset for the critical design parts gives vanishingly low failure risk.