ALT_LVDS timing fails for core clock

[Altera_Forum]

Hi, 

 I'm using Quartus 13.1 with a Stratix IV GX dev kit. Trying to implement a simple test design for a 6 bit deserialiser using ALT_LVDS Rx.  But I'm getting timing errors in a weird place.  The register at the outputs of the LVDS_Rx megafunction. The slow clock.  Timequest says the launch clock is the dast clock (480MHz). The latch clock is the slow clock (80MHz). And there are hold errors.   I don't see why these exist. Is there something wrong with the way I am reading them?  Its a simple design. 8 channels Lvds Rx with 6 bit deserialiser. Slow speeds. Feeds to a DC FIFO.. But I can't meet timing according to quartus..  Attached a couple of screenshots if it helps.  Thanks ZubairLK  https://www.alteraforum.com/forum/attachment.php?attachmentid=8454 https://www.alteraforum.com/forum/attachment.php?attachmentid=8455

[Altera_Forum]

--- Quote Start ---  The reference design that came with it had it disabled? If so, could you file an SR or attach a link to the project? That should not be the case, and is cruel to figure out.  --- Quote End ---   Yes. Submitted an SR.  Edit : http://www.altera.co.uk/products/devkits/altera/kit-siv-gx.html This kit. The 230 edition.