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Valued Contributor III

ALTDDIO / DDIO w/ Gated Input Clock in Stratix III

Hi, all. I'm still in schematic design for a project that requires a DDR input interface running at ~400Mbps (single lane, ~200MHz clock rate, ~400MHz data toggle) to a Stratix III device. The interface consists of a clock, data (4x), and a frame bit, with the data/frame either centered w/ respect to the clock or edge-aligned. The kicker is that the clock/data will always run at the fastest possible rate, and when there aren't full frames of data, the clock and data will be gated. 


I'm wondering if there's any reason that I couldn't run a standard ALTDDIO in receive mode, with the module itself not being any the wiser that the clock is being gated to it. I realize that I'd have to bypass any sort of ALTPLL module for the clock, because it would unlock during the periods in which the clock is not present. If the data is centered over the clock (good eye), then I should be good for setup/hold, as long as the PCB traces are matched. Any thoughts on this?  


My other option, I believe, would be to use ALTLVDS at a 4x rate and oversample the edge-aligned clock and data, and make determinations in a state machine about where my valid data is. The problem is that I would need the RX CLK pins routed to GCLKs for the ALTDDIO method and to standard LVDS RX pins for the ALTLVDS method. Will likely put in hooks for doing either method, but just thought I would toss this out there, in case someone's done it before. 


Any input would be appreciated! 


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