Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
21615 Discussions

ALTDQ DQS2 Design Example for Cyclone V

mkbonn
Novice
1,497 Views

Hi, I am aware that there is an altdq dqs Design Example for StratixV and ArriaV.

Does anyone knows of an altdq dqs Design Example for Cyclone V?

Thanks

 

0 Kudos
1 Solution
mkbonn
Novice
1,448 Views
0 Kudos
5 Replies
KennyTan_Altera
Moderator
1,466 Views

Any update?


0 Kudos
mkbonn
Novice
1,462 Views

Hi, Thanks for the pointer. It is not a straightforward task to migrate from StratixV to Cuclone V. The dq_dqs2 modules are not exactly compatible.   I might dedicate more time to it at a later stage.

 

It would be useful if Intel publish a reference design for Cyclone V and altdq_dqs2 module.

 

Thanks again

0 Kudos
KennyTan_Altera
Moderator
1,451 Views

Sure, I will put this as internal request. As for now, user will have to work on it.


0 Kudos
mkbonn
Novice
1,449 Views

Thank you. This is much appreciated !

0 Kudos
Reply