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Hello,
I perform an RTL simulation (ModelSim) of an ALTGX transmitter-only for an Arria II GX. The transmitter is set to take a 20-bit input. I use Basic mode, 4 lanes unbonded. After I release powerdown and resets the proper way (see attachment), the PLL will lock normally. The problem is that the ALTGX ignores the 20-bit data I feed to its input and goes on outputting over and over K28.5- (0101111100). Help!Link Copied
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I have found a solution to my problem. On the contrary to what is told in the A2GX manual (Figure 4-3), tx_digitalreset must NOT be deasserted right after pll_locked goes to 1 but some delay must be added.
I delayed 16 clocks (@ 100 MHz) tx_digitalreset deassertion after pll_locked goes high. The ALTGX now quits outputting K.28.5- and K.28.6- and starts outputting the real data I am feeding to it. Great that I found it, sad that, once again, I'm losing time fixing somebody else's bugs.- Mark as New
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The same problem with simulating altgx 3gb/s 1 lane 16bit+8b/10b basic mode transmitter+receiver cyclone iv gx.
The receiver works fine after correct initialization procedure, transmitter do not. I have added pause, like you, but no success, it is in stuck state. The initializing procedure: (timescale = 1ps)initial begin
gxb_powerdown <= 0;
pll_areset <= 0;
rx_analogreset <= 0;
rx_digitalreset <= 0;
tx_digitalreset <= 0;
# 10000 gxb_powerdown <= 1;
pll_areset <= 1;
rx_analogreset <= 1;
rx_digitalreset <= 1;
tx_digitalreset <= 1;
# 1000000 pll_areset <= 0;
gxb_powerdown <= 0;
wait( pll_locked) repeat( 300) @ (posedge tx_clkout);
tx_digitalreset <= 0;
wait( ~busy) repeat( 3) @ (posedge tx_clkout);
rx_analogreset <= 0;
wait( rx_freqlocked)# 4000000 rx_digitalreset <= 0;
end
This - "wait( pll_locked) repeat( 300) @ (posedge tx_clkout)" do not help. There is no required pause in handbook's description.
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Got it done.
It was just a misprint in TB code.
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