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Beginner
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ALTLVDS_RX input clock jitter mitigation

We are using ALTLVDS_RX on a Arria V type FPGA to receive data from a MIPI D-PHY device as described in https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an754.pdf

In this particular configuration, we are receiving MIPI at 300 MHz (600 Mbps) on 2 data lanes (and 1 clock lane). The differential MIPI clock is connected to ALTLVDS_RX input clock port. For ALTLVDS_RX we are using the following configuration when generating from the GUI.

  • Number of channels is 4
  • Deserialization factor is 8
  • No external PLL
  • Input clock rate 300 MHz
  • "Use 'pll_areset' input port" enabled
  • "Use 'rx_locked' output port" enabled
  • "Regional clock" for 'rx_outclock' clock resource
  • 90deg phase alignment of 'rx_in' with respect to 'rx_inclock'
  • "Register outputs" enabled

With this setup we can normally successfully receive from MIPI D-PHY device.

However, we occassionally get bit errors in the data received which results in ECC/CRC errors on MIPI level. We have performed board level measurments and found a correlation between occurrance of ECC/CRC errors and increased jitter in the MIPI clock (ALTLVDS_RX input clock). Interestingly, the ALTLVDS_RX PLL maintains its lock status in this case, but there is probability that some bits are not transmitted properly.

We have the following questions

  1. Is it feasible for input clock jitter on ALTLVDS_RX to lead to false capturing of the input data while the PLL maintains its lock? We are currently assuming that jitter on ALTLVDS_RX input clock has some effect on ALTLVDS_RX output clocks which leads to the capturing errors.
  2. Are there any ALTLVDS_RX settings that we can make to mitigate the effect of jitter in the input clock? We were also thinking of using ALTLVDS_RX in "external PLL mode" so we have more control over specific PLL settings.

Thanks

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Moderator
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Re: ALTLVDS_RX input clock jitter mitigation

Hi User Von SCS

Sorry for late response due to long holiday here.

May I know if you are currently using the ALTLVDS with DPA or non-DPA mode? 

By referring to doc below:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altlvds.pdf

Section 1.5.3.1 explaining the DPA operation each time the DPA shifts the phase taps during normal operation to track variations between the relationship of the reference clock source and the data. Depending on different FPGA family, the reset mechanism would be different. 

Let me know if this help in your issue.

Thanks.

Eng Wei

 

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Beginner
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Re: ALTLVDS_RX input clock jitter mitigation

Hi Eng Wei

thanks for your reply.

We are using ALTLVDS_RX in non-DPA mode.

Thanks

 

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Moderator
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Re: ALTLVDS_RX input clock jitter mitigation

Hi User Von SCS

Are you able to try out DPA mode to overcome your design issue?

 

Thanks.

Eng Wei

 

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Beginner
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Re: ALTLVDS_RX input clock jitter mitigation

Hi Eng Wei

I only have limited understanding of the ALTLVDS_RX DPA mode.

We are seeing spurious clock jitter at the ALTLVDS_RX clock input which in turn seems to cause wrong acquisiton of the data (ALTLVDS_RX PLL lock remains). So "usually" transmission is working fine, and only sometimes this clock jitter occurs in the transmitting device for a short time causing CRC errors. Ideally we want to avoid CRC completely in this case.

Can DPA mode be used to solve this kind of problem?

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Moderator
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Re: ALTLVDS_RX input clock jitter mitigation

Hi User Von SCS

It really depends on how the jitters look like. If it is a phase shift, it will work. If the clock is heavily distorted, then problem might still exist. 

Using external PLL allowing us to control parameters like bandwidth setting, it might or might not help depends on the jitters behaviour. 

The best solution is still fixing the source that is causing the jitters, as a clean source is important to feed FPGA.

Meanwhile, I will be off for a week from now. Allow me some time to get back to you if you have further question.

 

Thanks. 

Eng Wei

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