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Constrain DQS to memory clock for DDR memory



I am building a DDR controller on a Cyclone 10 LP device. Using various guides I have managed to constrain the DQ signals to the DQS clock for write operations. However now I am trying to figure out how to properly constrain DQS to the memory clock. The memory chip I am interfacing requires that the DQS rising edge is within +-90° of the rising edge of the memory clock. 

According to intel guide an433.pdf p7 and other sources I have read online, it is customary to implement DQS as a ALTDDIO_OUT megafunction so that the datapath closely matches the path of DQ. I have implemented the DQS datapath like so and according to the logic analyzer, DQS is sufficiently in phase with the memory clock to meet spec (on the bench). I can also successfully read and write to the memory without using any constraints on DQS. However, I would like to constrain DQS to the memory clock so that quartus will raise a timing exception when DQS is out of spec.

I have tried to treat DQS as data, and the memory clock as the clock in order to constrain the data strobe in the following way:

create_generated_clock -source [get_pins $pll_clk] -name gen_mem_clk [get_ports {mem_clk}]
set_output_delay -clock gen_mem_clk -max [expr -$T_quart] [get_ports {mem_dqs[*]}]
set_output_delay -clock gen_mem_clk -min [expr -$T + $T_quart] [get_ports {mem_dqs[*]}]

where T is the clock period, T_quart is a quarter of the clock period and pll_clk is an alias for the PLL generated clock that drives mem_clk (and mem_dqs) from derive_pll_clocks.

This assumes the DQS signal will be latched by the clock at the next mem_clk edge, which makes the fitter delay the DQS signal by an unwanted amount. I have unsuccessfully tried several variations with set_multicycle_path from $pll_clk to gen_mem_clk in an attempt to shift the launch and latch edge backwards. 

I can't find information online on how to constrain DQS to the memory clock, nor can I find information on constraining two output clocks to each other. So my question is, how do I properly constrain one output clock to be within a certain phase of another output clock?


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4 Replies
Honored Contributor III

Before diving into this in detail, is there a reason why you are not using memory IP to implement at least the PHY for this interface?  You can still build your own controller if you want, but this generates the timing constraints you need on the I/O.



AFAIK the memory controller is not compatible with LPDDR ram modules which I am using, and DDR memory in general isn't supported on cyclone 10 LP devices. The PHY isn't available in the IP library if you target a cyclone 10 LP device.

"Even though the Intel Cyclone 10 LP I/O buffers support various I/O standards for memory
application, Intel does not validate nor support any IP that is intended for memory
applications such as DDR or DDR2."

I am also generally interested in constraining two output clocks to each other, the memory controller is just the application.



Unfortunately, there is no constraint to constrain a clock signal wrt to another clock signal. You have to apply multicycle exception if needed.


Best regards,




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Best regards,