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ALTLVDS TX IP - pin location constraints

kikoss
New Contributor I
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Hello 


I Instantiated on my design an ALTLVDS TX module  for agilex7 , and the compilation passed 

This ALTLVDS TX  module output 4 differential ports (configured to 192Mbps each one )  + 1 differential CLK 

I constraint those 4 data ports + 1 CLK  port to be located whithin  differential I/O  , 2F bank as the following : 

set_location_assignment IOBANK_2F -to TX_LVDS_ADC_1N
set_location_assignment IOBANK_2F -to TX_LVDS_ADC_1P
set_location_assignment IOBANK_2F -to TX_LVDS_ADC_2N
set_location_assignment IOBANK_2F -to TX_LVDS_ADC_2P
set_location_assignment IOBANK_2F -to TX_LVDS_ADC_3N
set_location_assignment IOBANK_2F -to TX_LVDS_ADC_3P
set_location_assignment IOBANK_2F -to TX_LVDS_ADC_4N
set_location_assignment IOBANK_2F -to TX_LVDS_ADC_4P

set_location_assignment IOBANK_2F -to TX_ADC_Data_Clock_P
set_location_assignment IOBANK_2F -to TX_ADC_Data_Clock_N

 

However the fiitter stage failed and thats the mesg : 

 

Error(175020): The Fitter cannot place logic pin in region (226, 0) to (240, 0), to which it is constrained, because there are no valid locations in the region for logic of this type.
Info(14596): Information about the failing component(s):
Info(175028): The pin name(s): TX_LVDS_ADC_1P
Info(175015): The I/O pad TX_LVDS_ADC_1P is constrained to the region (226, 0) to (240, 0) due to: User Location Constraints (IOBANK_2F)
Info(14709): The constrained I/O pad is contained within this pin

 

kikoss_0-1717654541653.png

 

Mean that I give quartus to choose exact  PIN location ,  but quartus don't accept the fact that those PINS are connected to bank2F 

 

Where can I find out what are the detailed rules quartus follows so i can apply appropriate constraint ? 

 

Thx 

Kikoss

 

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FvM
Valued Contributor III
229 Views

Hi,
did you assign LVDS IO standard? Did you try to assign explicite pin locations for differential pairs? You only need to assign positive pins, negative pin will be assigned by fitter automatically.

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FvM
Valued Contributor III
230 Views

Hi,
did you assign LVDS IO standard? Did you try to assign explicite pin locations for differential pairs? You only need to assign positive pins, negative pin will be assigned by fitter automatically.

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kikoss
New Contributor I
174 Views

Hello 

 

You right , need to set IO standard , seems quartus use default for ALTLVDS RX IP but not for ALTLVDS TX IP 

 

Here is the standard I set : 


set_instance_assignment -name IO_STANDARD "TRUE DIFFERENTIAL SIGNALING" -to CLKINP -entity safety_top_level
set_instance_assignment -name IO_STANDARD "TRUE DIFFERENTIAL SIGNALING" -to TX_LVDS_ADC_2P -entity safety_top_level
set_instance_assignment -name IO_STANDARD "TRUE DIFFERENTIAL SIGNALING" -to TX_LVDS_ADC_3P -entity safety_top_level

THX 

 

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AqidAyman_Intel
Employee
142 Views

Hello,


Did the issue resolved after you assign the differential I/O standard for the pins?


Regards,

Aqid


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kikoss
New Contributor I
127 Views

 Hello Yes, I accept it as solution ... 

 

THX 

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AqidAyman_Intel
Employee
24 Views

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you.


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