I need to simulate the 2x 4-channel 40MHz, 16 bits ADCs with serialized ouput (each chip with D0,D1,D2,D3,frame and clock signal). The ALTLVDS_TX seems to be a good choice that serialize the ADC data (16 bits data needs to be divided to 2 Bytes and can be configured to DDR output mode). For LVDS clock output from PLL block, it needs to be connected the special FPLL_TL_CLKOUT pins(only 4 pairs available with my device). I want to know if the clock_out signal from the ALTLVDS_TX also needs to be assigned this FPLL_TL_CLKOUT pins.
