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Altera_Forum
Honored Contributor I
976 Views

ALTLVDS does not seem to use DDIO/DDR with its PLL clock?

Hello, 

 

I am trying to create and compile an ALTLVDS megafunction for 4 lanes, of deserialisation factor 7, frequency 74.25, as such data rate 519.75. I have the Cyclone V: 5CGXFC4C7U19C8 device set to compile for. The Cyclone V device handbook(page 40) states that the maximum PLL output frequency for internal clocks is 460 MHz for that device. 

 

When I try to compile the megafunction I get the following error: 

Error: PLL Output Counter parameter 'output_clock_frequency' is set to an illegal value of '519.75 MHz' on node ... 

 

This solution(https://www.altera.com/support/support-resources/knowledge-base/solutions/rd08292014_38.html) states it is because the device does not support the speed of PLL I require. 

 

This would be alright if the ALTLVDS megafunction used single data rate to process the data. 

 

However, in the LVDS SERDES Transmitter/Receiver IP Cores User Guide, page 3 it says:  

"The Cyclone series uses DDIO registers as part of the SERDES interface. Because data is clocked on both the rising edge and falling edge, the clock frequency must be half the data rate; therefore, the PLL runs at half the frequency of the data rate." 

 

As such, the "output_clock_frequency" should be 259.875, which is well within the allowed speed range. 

 

Should I use the External PLL option to enable DDR processing? What am I missing? 

 

Regards, 

Tibor
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3 Replies
Altera_Forum
Honored Contributor I
86 Views

For devices before Cyclone V, there was no true SERDES and it had to use DDIO registers. The problem is that this solution gets slower and slower at smaller geometries(due to larger On-Die Variation). Because of that Cyclone V has the dedicated SERDES and dedicated altlvds clock tree. For this implementation, it uses a dedicated clock tree for the fast clock that only drives the SERDES. To get better performance it uses a single register to capture the data, and the clock runs at the full data rate(this avoids rise/fall variation, thereby improving performance).  

The Cyclone V -8 altlvds receiver is spec'd to run at 640Mbps, and so the clock from the PLL that drives the altlvds clock tree runs this fast. (The PLL output frequency max is probably a factor of how fast a global clock tree can run, not this altlvds). So what you're doing sounds right and I am fairly certain should work. 

(If you go to a serialization of /2, it will use the DDIO and a global clock tree, so the clock rate will be cut in half, but once you start entering timing constraints it will fail timing, so I would avoid that)
Altera_Forum
Honored Contributor I
86 Views

I quickly threw this project together in Q16.1 with a 600Mbps altlvds receiver in CV -8. No errors.

Altera_Forum
Honored Contributor I
86 Views

Hello, 

 

Thanks for the quick response and sorry for me replying so late. I have tried to recreate the configuration you wrote and I failed, till by trial and error I realised that the problem was that I set an illegal phase shift value. It did not pop up in the error messages, so I guessed it wasn't the problem. 

 

Now that I carefully read this solution https://www.altera.com/support/support-resources/knowledge-base/solutions/rd09202013_385.html , the megafunction compiles. 

 

Thank you for your help.
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