ALTLVDS external clock

[Altera_Forum]

Hi all, 

I'm trying to implement the ALTLVDS_RX in a cyclone V. i would to connect the rx_enable and the rx_inclock to a fpga i/o (lvds dedicate input clock pins). is it possible?  For now I'm stuck to the error: "error: ir fifo userdes block node 'lvds_rx:lvds_rx_inst0|altlvds_rx:altlvds_rx_component|lvds_rx_lvds_rx:auto_generated|sd2' is not properly connected on the 'writeclk' port.  it must be connected to one of the valid ports listed below.  info: can be connected to loaden port of arriav_pll_lvds_output wysiwyg  info: can be connected to outclk port of generic_pll wysiwyg  info: can be connected to lvdsclk port of cyclonev_pll_lvds_output wysiwyg info: can be connected to outclk port of arriav_clkena wysiwyg (https://www.altera.com/support/support-resources/knowledge-base/solutions/rd02152013_340.html)"  If I use the relate solution (https://www.altera.com/support/support-resources/knowledge-base/solutions/rd04102013_389.html), my quartus crash during the synthesis. I think that the primitive cyclonev_pll_lvds_output needs a pll, but I have not a pll before the ALTLVDS_RX.   So, the question is: can i use an altlvds_rx without pll?  Thank you.

[Altera_Forum]

Hi, 

 It seems that you are trying to build an LVDS application with external clock.   You can reference to the LVDS Userguide IP under the external clock chapter  https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_altlvds.pdf  I believe there should be a section with a guidelines on how to set the following 3 things you had mentioned --> LOADEN, OUTCLK, LVDSCLK

[Altera_Forum]

There is a parameter editor allow you to choose the "Use External PLL option". 

You can refer to the ALTLVDS IP core in external PLL mode from LVDS user guide for more details.

[Altera_Forum]

you are seeing the bunch of errors because you didnt put in a buffer. 

Refer to below kdb: https://www.altera.com/support/support-resources/knowledge-base/solutions/rd04102013_389.html  It will teach you how to put in the buffers. The error will go away after that.

[Altera_Forum]

Hi all, 

 dear ah_zhi02,  when you talk about "the external clock chapter" are you referring to "ALTLVDS IP Core in External PLL Mode" p. 62?  I have not found an external clock chapter and the guidelines p 62 are for the external pll. I don't want to use any pll. All my clocks are generated externally to the FPGA.  dear irish, I'm already using the External PLL option but the clock that I want to use are coming from a FPGA pin. They are not coming from a pll.  dear nicejob, I have already used the solution https://www.altera.com/support/suppo...02013_389.html. The problem is that I think that the primitive cyclonev_pll_lvds_output needs a pll, but I have not a pll before the ALTLVDS_RX. When I use a cyclonev_pll_lvds_output my quartus crash during the synthesis.

[Altera_Forum]

The clock must come from a PLL. These are dedicated paths laid out for minimal skew/max performance. This allows the dedicated LVDS circuitry to run at a much higher rate, although it loses some flexibility. 

(There are three outputs from the PLL that must be in sync with each other, the high-speed clock, the low-speed clock, and the load enable signal. I'm not sure how you're planning on doing this without a PLL).