ALTPLL's problem

[Altera_Forum]

I'm using a ATLPLL IP In my design. This PLL has one input clock, one areset, one Lock output and one output clock. 

The input clock is 50MHz (I wrote 45MHz) . The PLL outputs should be 100MHz. The code is not working (after reset I get the following meassage:"# ** Fatal: (SIGFPE) Floating point exception").  The ALTPLL's connections as below:   PLL port map ( areset => reset, --constant '0' inclk0 => CLOCK_50,  c0 => PLL100MHz, --100Mhz expected clock locked => locked); The ALTPLL's setting is below:   bandwidth_type => "AUTO", clk0_divide_by => 9, clk0_duty_cycle => 50, clk0_multiply_by => 20, clk0_phase_shift => "0", compensate_clock => "CLK0", inclk0_input_frequency => 22222, intended_device_family => "Cyclone III", lpm_hint => "CBX_MODULE_PREFIX=PLL", lpm_type => "altpll", operation_mode => "NORMAL", pll_type => "AUTO", port_activeclock => "PORT_UNUSED", port_areset => "PORT_USED", port_clkbad0 => "PORT_UNUSED", port_clkbad1 => "PORT_UNUSED", port_clkloss => "PORT_UNUSED", port_clkswitch => "PORT_UNUSED", port_configupdate => "PORT_UNUSED", port_fbin => "PORT_UNUSED", port_inclk0 => "PORT_USED", port_inclk1 => "PORT_UNUSED", port_locked => "PORT_USED", port_pfdena => "PORT_UNUSED", port_phasecounterselect => "PORT_UNUSED", port_phasedone => "PORT_UNUSED", port_phasestep => "PORT_UNUSED", port_phaseupdown => "PORT_UNUSED", port_pllena => "PORT_UNUSED", port_scanaclr => "PORT_UNUSED", port_scanclk => "PORT_UNUSED", port_scanclkena => "PORT_UNUSED", port_scandata => "PORT_UNUSED", port_scandataout => "PORT_UNUSED", port_scandone => "PORT_UNUSED", port_scanread => "PORT_UNUSED", port_scanwrite => "PORT_UNUSED", port_clk0 => "PORT_USED", port_clk1 => "PORT_UNUSED", port_clk2 => "PORT_UNUSED", port_clk3 => "PORT_UNUSED", port_clk4 => "PORT_UNUSED", port_clk5 => "PORT_UNUSED", port_clkena0 => "PORT_UNUSED", port_clkena1 => "PORT_UNUSED", port_clkena2 => "PORT_UNUSED", port_clkena3 => "PORT_UNUSED", port_clkena4 => "PORT_UNUSED", port_clkena5 => "PORT_UNUSED", port_extclk0 => "PORT_UNUSED", port_extclk1 => "PORT_UNUSED", port_extclk2 => "PORT_UNUSED", port_extclk3 => "PORT_UNUSED", self_reset_on_loss_lock => "OFF", width_clock => 5     What's wrong with my design?  Idan

[Altera_Forum]

The ALTPLL must have "reset" at the beginning.  

Sim resolution must be: "ps":-P