ALUTS imbalance

[Altera_Forum]

I am implementing floating point square root by long hand square root method. in order to decrease the latency of the algorithm, i remove in between register stages from the RTL. Now the problem is, when i remove the registers/flipflops between the logic and synthesize it, i experienced an increase in Number of ALUTs with the decrease in Fmax and number of registers( as both were expected to be decreased). My question is why the number of ALUTs increases when i remove registers between the logic, as i only supposed the decrease in regs and fmax. Paste below is part of the parametrizable code that was designed to run with 27 latency and 16 latency. 

 with longer latency ALUT 419 REG(s) 1101 with reduced latency ALUT 610 REG(s) 611  Interestingly, doing the same synthesis with Xilinx reduces the registers by half (715 to 487), but keeps the combinatorial slice LUT(s) almost the same (1127 to 1016), infact a reverse effect compared to xilinx.  The clock constraint was deliberately changed to real low 10 Mhz for both cases, and still the effect remained the same. The question arises in what cases removing registers results in increase of synthesized logic due to cascading of combinatorial logic?  module fix_sqrt_rtl (  input clk, input [31:0] opa,  output reg [24:0] res_stg25 );  reg [49:0] inp;  `ifdef LATENCY27 always @(posedge clk)  inp = opa[23] ? {1'b0,1'b1, opa[22:0], 25'd0}/*even*/ : {1'b1, opa[22:0], 26'd0}/*odd*/; `else always @(posedge clk)  inp <= opa[23] ? {1'b0,1'b1, opa[22:0], 25'd0}/*even*/ : {1'b1, opa[22:0], 26'd0}/*odd*/; `endif  //==============stage 1============== reg [1:0] rem_stg1; reg [47:0] inp_stg1;  always @(*)  begin  {rem_stg1[1:0]} = {inp[49:48]} - 2'b01;  inp_stg1 = inp[47:0];  end //==============stage 2============== reg res_stg1; reg [2:0] rem_stg2; reg [45:0] inp_stg2; reg sign2; `ifdef LATENCY27 always @(posedge clk)  {sign2, rem_stg2[2:0]} <= {rem_stg1[1:0], inp_stg1[47:46]} - 4'b0101;  always @(posedge clk)  inp_stg2[45:0] <= inp_stg1[45:0]; `else always @(*)  {sign2, rem_stg2[2:0]} = {rem_stg1[1:0], inp_stg1[47:46]} - 4'b0101;  always @(*)  inp_stg2[45:0] = inp_stg1[45:0]; `endif  //==============stage 3============== reg [1:0] res_stg2; reg [3:0] rem_stg3; reg [43:0] inp_stg3; reg sign3;  `ifdef LATENCY27 always @(posedge clk)  res_stg2[1:0] <= {1'b1, !sign2};  always @(posedge clk)  {sign3, rem_stg3[3:0]} <= {rem_stg2[2:0], inp_stg2[45:44]} + ({5{!sign2}} ^ {1'b0, 1'b1, !sign2, sign2, 1'b1}) + !sign2;  always @(posedge clk)  inp_stg3 <= inp_stg2[43:0]; `else always @(*)  res_stg2[1:0] = {1'b1, !sign2};  always @(*)  {sign3, rem_stg3[3:0]}= {rem_stg2[2:0], inp_stg2[45:44]} + ({5{!sign2}} ^ {1'b0, 1'b1, !sign2, sign2, 1'b1}) + !sign2; `endif //==============stage 4============== reg [2:0] res_stg3; reg [4:0] rem_stg4; reg [41:0] inp_stg4; reg sign4;  `ifdef LATENCY27 always @(posedge clk)  res_stg3[2:0] <= {res_stg2[1:0], !sign3};  always @(posedge clk)  {sign4, rem_stg4[4:0]} <= {rem_stg3[3:0], inp_stg3[43:42]} + ({6{!sign3}} ^ {1'b0, res_stg2[1:0], !sign3, sign3, 1'b1}) + !sign3;  always @(posedge clk)  inp_stg4[41:0] <= inp_stg3[41:0]; `else always @(*)  res_stg3[2:0] = {res_stg2[1:0], !sign3};  always @(*)  {sign4, rem_stg4[4:0]} = {rem_stg3[3:0], inp_stg2[43:42]} + ({6{!sign3}} ^ {1'b0, res_stg2[1:0], !sign3, sign3, 1'b1}) + !sign3;  always @(*)  inp_stg4[41:0] = inp_stg2[41:0]; `endif  //==============stage 5============== reg [3:0] res_stg4; reg [5:0] rem_stg5; reg [39:0] inp_stg5; reg sign5;  always @(posedge clk)  res_stg4[3:0] <= {res_stg3[2:0], !sign4};  always @(posedge clk)  if (!sign4)  {sign5, rem_stg5[5:0]}<= {rem_stg4[4:0], inp_stg4[41:40]} - {1'b0, res_stg3[2:0], !sign4, sign4, 1'b1};  else  {sign5, rem_stg5[5:0]}<= {rem_stg4[4:0], inp_stg4[41:40]} + {1'b0, res_stg3[2:0], !sign4, sign4, 1'b1};  always @(posedge clk)  inp_stg5[39:0] <= inp_stg4[39:0];  //==============stage 6============== reg [4:0] res_stg5; reg [6:0] rem_stg6; reg [37:0] inp_stg6; reg sign6;  `ifdef LATENCY27 always @(posedge clk)  res_stg5[4:0] <= {res_stg4[3:0], !sign5};  always @(posedge clk)  if (!sign5)  {sign6, rem_stg6[6:0]} <= {rem_stg5[5:0], inp_stg5[39:38]} - {1'b0, res_stg4[3:0], !sign5, sign5, 1'b1};  else  {sign6, rem_stg6[6:0]} <= {rem_stg5[5:0], inp_stg5[39:38]} + {1'b0, res_stg4[3:0], !sign5, sign5, 1'b1};  always @(posedge clk)  inp_stg6[37:0] <= inp_stg5[37:0]; `else always @(*)  res_stg5[4:0] = {res_stg4[3:0], !sign5};  always @(*)  if (!sign5)  {sign6, rem_stg6[6:0]} = {rem_stg5[5:0], inp_stg5[39:38]} - {1'b0, res_stg4[3:0], !sign5, sign5, 1'b1};  else  {sign6, rem_stg6[6:0]} = {rem_stg5[5:0], inp_stg5[39:38]} + {1'b0, res_stg4[3:0], !sign5, sign5, 1'b1};  always @(*)  inp_stg6[37:0] = inp_stg5[37:0]; `endif  //==============stage 7============== reg [5:0] res_stg6; reg [7:0] rem_stg7; reg [35:0] inp_stg7; reg sign7;  always @(posedge clk)  res_stg6[5:0] <= {res_stg5[4:0], !sign6};  always @(posedge clk)  if (!sign6)  {sign7, rem_stg7[7:0]}<= {rem_stg6[6:0], inp_stg6[37:36]} - {1'b0, res_stg5[4:0], !sign6, sign6, 1'b1};  else  {sign7, rem_stg7[7:0]}<= {rem_stg6[6:0], inp_stg6[37:36]} + {1'b0, res_stg5[4:0], !sign6, sign6, 1'b1};  always @(posedge clk)  inp_stg7[35:0] <= inp_stg6[35:0];   //==============stage 8============== reg [6:0] res_stg7; reg [8:0] rem_stg8; reg [33:0] inp_stg8; reg sign8;  `ifdef LATENCY27 always @(posedge clk)  res_stg7[6:0] <= {res_stg6[5:0], !sign7};  always @(posedge clk)  if (!sign7)  {sign8, rem_stg8[8:0]} <= {rem_stg7[7:0], inp_stg7[35:34]} - {1'b0, res_stg6[5:0], !sign7, sign7, 1'b1};  else  {sign8, rem_stg8[8:0]} <= {rem_stg7[7:0], inp_stg7[35:34]} + {1'b0, res_stg6[5:0], !sign7, sign7, 1'b1};  always @(posedge clk)  inp_stg8[33:0] <= inp_stg7[33:0]; `else always @(*)  res_stg7[6:0] = {res_stg6[5:0], !sign7};  always @(*)  if (!sign7)  {sign8, rem_stg8[8:0]} = {rem_stg7[7:0], inp_stg7[35:34]} - {1'b0, res_stg6[5:0], !sign7, sign7, 1'b1};  else  {sign8, rem_stg8[8:0]} = {rem_stg7[7:0], inp_stg7[35:34]} + {1'b0, res_stg6[5:0], !sign7, sign7, 1'b1};  always @(*)  inp_stg8[33:0] = inp_stg7[33:0]; `endif  //==============stage 9============== reg [7:0] res_stg8; reg [9:0] rem_stg9; reg [31:0] inp_stg9; reg sign9;  always @(posedge clk)  res_stg8[7:0] <= {res_stg7[6:0], !sign8};  always @(posedge clk)  if (!sign8)  {sign9, rem_stg9[9:0]}<= {rem_stg8[8:0], inp_stg8[33:32]} - {1'b0, res_stg7[6:0], !sign8, sign8, 1'b1};  else  {sign9, rem_stg9[9:0]}<= {rem_stg8[8:0], inp_stg8[33:32]} + {1'b0, res_stg7[6:0], !sign8, sign8, 1'b1};  always @(posedge clk)  inp_stg9[31:0] <= inp_stg8[31:0]; . . . . endmodule