Timer Interrupts with Nios II

[Altera_Forum]

Hello guys, 

 I am using the DE0 board and I want to implement a timer interrupt to trigger a PWM signal every 1 ms. The DE0 board has a cyclone III and I use Quartus II (ver 9.1sp2) & NIOS II (ver 9.1). I have setup the nios system as given in NIOS II hardware tutorial.   I tried to run a timer interrupt C code from the interrupt example as given in the University Program. The program compiles. However, when I try to run it I get the following error message.   ----------------------------------- Using cable "USB-Blaster [USB-0]", device 1, instance 0x00 Pausing target processor: OK Reading System ID at address 0x00011088: verified Initializing CPU cache (if present) OK Downloading 00000020 ( 0%) Downloading 00008000 ( 0%) Downloaded 8KB in 0.1s  Verifying 00000020 ( 0%) Verify failed between address 0x20 and 0x43 Leaving target processor paused ----------------------------------   Why do I get this error message? How can I address this problem. Thanks in advance.

[Altera_Forum]

Verify failed between address 0x20 and 0x43 

======================================= You should check the address on the Nios2 system you build. I guess, between 0x20 and 0x43 address, you may place an SDRAM. If that, you can assign a pin for SDRAM_CLK.You can get SDRAM_CLK from PLL.

[Altera_Forum]

Hi, 

 yes he´s right. The problem seems to come with wrong SDRAM settings!