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AXI3 & Bank of Registers implementation

Altera_Forum
Honored Contributor II
‎12-03-2015 01:44 PM
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Hi All, 

 

I need to connect a bank of registers (let's say 10 registers) to the AXI3 lightweight bus (I'm working with ArriaV SX).  

 

How can I do so? Does Altera has an appropriate IP, which can be connected to AXI3 from one side and from another side provide a convenient access to the registers? I believe I don't need to use an On-chip RAM for just 10 registers...  

 

Thank you
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Altera_Forum
Honored Contributor II
‎12-09-2015 02:04 PM
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Are there any comments? Should i use a Parallel I/O for that purpose? But it implements just a single register... So, if I need 20 registers then I need to instantiate the Parallel I/O 20 times? What will happen when I'll need to implement 50 registers? 100 registers?

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