Problem with dynamic PLL reconfiguration

[Altera_Forum]

I am working on a project which involves dynamically configuring PLL to different frequencies. 

I have written a VHDL code for my requirement, however I am facing some circumstances in simulation which I am not able to comprehend. When I give a reset to the PLL I expect clock to be 0 and locked signal to be 0 immediately. However I find that lock signal doesnt reset at all. This would affect my design as out of range clocks might get into my logic and system might just crash.  I have attached simulation snapshot.  Please help.

[Altera_Forum]

What does resetn_sig refer to in your design? Seems like this signal is not valid in the simulation.

[Altera_Forum]

Hi Nic, 

 In the snapshot above rst_usr is the signal that is input as reset to PLL.  For better clarity I have attached another snapshot with pll rst, lock and pll output clock coloured in yellow. Note that lock is not getting low even after reset is asserted.