About converting two sof files to one jic file

[Altera_Forum]

Hi, I encountered some difficulties in creating jic file and need help. 

I have two sof files and two jic files generated based on the sof file, either one jic works well after I program it into EPCS device, then I tried to combine the two sof files to a single jic file, the generating process is showed in the attached picture. But FPGA cannot boot from EPCS at all, I thought the two sof files were just saved in different areas of EPCS device, and FPGA will start from the 0 address of EPCS device, but it seems my idea is wrong, there must be some connections between the two sof files. Is there anybody clear about the issue? thanks a lot.

[Altera_Forum]

First of all - you should read about the JTAG Indirect Programming in the an370: using the serial flashloader with the quartus ii software (http://www.altera.com/literature/an/an370.pdf) 

 Check the address settings during sof to jic convertation. Your sof files can overlap each other. The uncompressed bitstream for the EP3C40 has 9600000 bits ([url]http://www.altera.com/literature/hb/cyc3/cyc3_ciii51016.pdf (http://www.altera.com/literature/hb/cyc3/cyc3_ciii51016.pdf)[/URL], page 9-7).  It is 1200000 bytes. The result of compression is unpredictable, it depends on your design. So, it can happend that the start address of the second sof (0x060000) is overlap the first sof.  P.S. Don't duplicate your questions, please...

[Altera_Forum]

Hi, Stewart, thanks a lot! 

apologized for duplicating question..  About the address, I'm sure they are not overlaped because I checked the generated map file. in fact, I use EPCS64 in my design, but I just post the image found in my computer, sorry for causing misunderstanding..  My another question, is remote update module is necessary for the two sof files case? e.g. if the factory image contains a remote update module, but there is no remote update module in app image, if force reconfig the app image, can the app will be loaded successfully?