About power management control of MAX10

[sawara]

I want to set it to sleep mode when it is not working to save the power consumption of MAX10.

I referred to the reference design, but I don't understand how to use PMC.

Power Management Controller | Design Store for Intel® FPGAs

I don't need ”gpio_pad_output[3:0]” or "cnt_value[7:0]/cnt_enter_sleep[7:0]/cnt_exit_sleep[7:0]" (User Logic) because I only want to suppress power when MAX10 is not operating.

Is it enough to connect "ioe" from PMC to IO Buffer(altera_gpio_lite) and "clk_ena" from PMC to Clock Control Block(clk_control_cltclkctrl)?
Do I need any connection from IO Buffer / Clock Control Block to my circuit?

Is power management of each GPIO automatically implemented from the IP of IO Buffer(altera_gpio_lite) under the control of ioe?
Similarly, is the power management of the global clock automatically implemented from the IP of Clock Control Block(clk_control_cltclkctrl) under the control of ena?

Please help me, thank you.

[EngWei_O_Intel]

Hi there

You need to enable the OE port of GPIO IP in order to connect IOE from PMC block. Similarly goes to clock control block where ena port need to be enabled.

You don't necessary to use all the ports mentioned. It depends on which part of your design need to be placed under power saving.

Thanks.

[sawara]

Hi,

Thank you for reply.

First of all, I want to reduce the core current.
I understand that I need to stop GCLK for that, is that correct?
Should I control clk_ena from PMC to clock control block(clk_control_altclkctrl)  to stop GCLK?

Then I want to reduce the IO current.
I understand that I need to stop GPIO for that, is that correct?
Should I control the ioe from PMC to IO Buffer(altera_gpio_lite) to stop GPIO?

Please let me know if there is anything else you need to control sleep other than the above.

Thanks.