About the BUFG specification in Intel FPGA.

[BXia]

Hi,

In xilinx FPGA, I see the BUFG specification for clock:

Does Intel FPGA has the BUFG specification too? Or what's the specification in Intel FPGA equivalent to BUFG, the GCLK or something else?

If Intel FPGA has BUFG, how many BUFGs in Arria 10 FPGA? Is it possible to see how many BUFG in Quartus software?

Thanks in advance.

[Farabi]

Hello,

I am sorry, Could you please explain what is BUFG, xilinx and intel terminology on buffer/io might be difference.

regards,

Farabi

[johnnyfan1979]

Hello Farabi,

Thanks for your reply.

Xilinx said BUFG is Global Clock Buffer：https://support.xilinx.com/s/article/24983?language=en_US , so I ask if BUFG is GCLK in Intel FPGA. If yes, how many BUFGs in Arria 10 FPGA? Is it possible to see how many BUFG by using Quartus software?

[BXia]

Hi Farabi, 

Thanks for your reply.

Xilinx said BUFG is Global Clock Buffer：https://support.xilinx.com/s/article/24983?language=en_US , so I ask if BUFG is GCLK in Intel FPGA. If yes, how many BUFGs in Arria 10 FPGA? Is it possible to see how many BUFG by using Quartus software?

[FvM]

Hello,
the equivalent term for Intel FPGA is GCLK. You find all details in Arria 10 Handbook, chapter 4 Clock Networks and PLLs in Intel Arria 10 Devices. Don't think i's appropriate to retell the document in this thread. Generally, Arria 10 has 32 GCLKs.

Quartus compilation report tells which resources are utilized for specific signals. Generally, it's rarely necessary or even useful to assign clock resources, e.g. clock control blocks in a design manually.

Regards

Frank

[AqidAyman_Intel]

Hi,

You can also learn more on the Global Clock Network for Arria 10 through this documentation. Refer to the link:

https://www.intel.com/content/www/us/en/docs/programmable/683461/current/global-clock-networks.html

Regards,

Aqid

[AqidAyman_Intel]

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