You will have to create a HPS2FPGA bridge and access the SDRAM via HPS from the FPGA side since the DDR is only connected to the HPS side on the DE0-Nano kit. The HPS should be used as a slave while the FPGA side will have a NIOS-2 as the master.
I thought the FPGA had a direct connection to the SDRAM controller (picture). In that case, I don't think using the SDRAM is a good idea.
Here are some details of my project:
I have designed an IP core that receives 4 consecutive bytes and concatenates them into a 32-bit word (basically a mux). I need to send the word somewhere so that the processor (running Linux) can pack the data and send it through Ethernet in UDP frames.
I have been reading some more about the Cyclone V and think that using an On-Chip RAM with two slave ports could be useful (FPGA writes while HPS reads). I am new to Intel SoCs so I am not sure if this is correct. Do you have any suggestions on how I can implement this system?
Link to picture