Accessing SDRAM from FPGA (DE0-Nano-SoC)

[DShat4]

Please, can someone explain me how to write data to the SDRAM from the FPGA?

Thank you

[Abe]

You will have to create a HPS2FPGA bridge and access the SDRAM via HPS from the FPGA side since the DDR is only connected to the HPS side on the DE0-Nano kit. The HPS should be used as a slave while the FPGA side will have a NIOS-2 as the master.

[DShat4]

Hello Abe,

I thought the FPGA had a direct connection to the SDRAM controller (picture). In that case, I don't think using the SDRAM is a good idea.

Here are some details of my project:

I have designed an IP core that receives 4 consecutive bytes and concatenates them into a 32-bit word (basically a mux). I need to send the word somewhere so that the processor (running Linux) can pack the data and send it through Ethernet in UDP frames.

I have been reading some more about the Cyclone V and think that using an On-Chip RAM with two slave ports could be useful (FPGA writes while HPS reads). I am new to Intel SoCs so I am not sure if this is correct. Do you have any suggestions on how I can implement this system?

EDIT:

Link to picture

https://www.google.com/search?q=cyclone+v&client=ubuntu&hs=Un7&channel=fs&source=lnms&tbm=isch&sa=X&ved=0ahUKEwjBwYS74qngAhUBxVkKHUD_B5UQ_AUIDigB&biw=1855&bih=982#imgrc=YCgN9iomG2xdlM:

[Fawaz_Al-Jubori]

Hello, You can use Nios II to write to HPS SDRAM. You need to connect the Data master of Nios II to the f2sdram bridge through the Address span extender. If you dont want to use a processor, you need to have a state-machine mechanism to write your data to SDRAM, however, this would be complex to verify. Thanks