Hello everyone!
I am trying to accelerate some computation by developing an accelerator in the FPGA. My idea is to replace the function invocation for a "hardware" invocation, passing some requiring values for the computations in hardware. Depending on the results of the hardware operation, some data should be move from one part of the memory to the other. In the current software implementation, pointers to the source and destination of the data are passed as parameters. My idea is that, once that the computation is done, the hardware accelerator perform the memory access to copy the required values. Is there any way to access the memory in a consistent/coherent way from FPGA and HPS? For example, that the address used for the HPS could be understandable/reachable by the FPGA.
I have searched for this in the Forum and other sources, but I no success yet finding an answer to this question. BTW, I am using the Cyclone V (DE1-SoC Board).
Thanks in advance. I really appreciate any insight about it!
