I am currently implementing the advanced SEU detection into my design and am having troubles finding (correct) information on these cores.
If you look at this document here (altera advanced seu detection ip core user guide (
https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_altadvseu.pdf)), the block diagram on page 3 shows a normal Avalon master interface. If you continue to go down to page 4, the table of signals does not list these correct signals! They are showing no Avalon master signals.
When i have the IP core instantiated in Qsys, I can see the Avalon master.
Now here is my bigger problem. I am not sure how to connect this Avalon master up to the ASMI located in the Qspi in order to check CRAM errors. There does not seem to be an interface connect that allows for this.
How am I supposed to set up SEU detection if I can not use the Avalon interface to check for SEU errors against the Sensitivity Lookup Information (SMH) stored in the external memory?
