Adder Nightmare!

[Altera_Forum]

Hi All, 

 I have been trying to create an adder array which is capable of adding three 10 bit numbers together. I have it working with unsigned numbers, but as soon as I try any signed numbers, the result is totally wrong. See images... https://alteraforum.com/forum/attachment.php?attachmentid=13525&stc=1 https://alteraforum.com/forum/attachment.php?attachmentid=13527&stc=1 https://alteraforum.com/forum/attachment.php?attachmentid=13528&stc=1   This is likely something simple to experienced users out there, so any help would be appreciated :)  Thanks.

[Altera_Forum]

Signed and unsigned arithmetic is the same. Your pictures are too small for me to really see.. are you sure you have the simulator set to view numbers as signed rather than unsigned?

[Altera_Forum]

I do have the simulator set to view as signed. I can't grasp why the error is arising, but positive signed numbers work absolutely fine, negative signed addition gives an incorrect answer.

[Altera_Forum]

Are you sure you have properly sign extended your inputs?

[Altera_Forum]

I have used the twos complement number system to carry out the sign operation on the input, this has been simulated and works correctly. An original unsigned input of 0 to 31 has been replaced with a signed input of 0 to -16 and 0 to +15.

[Altera_Forum]

You said the numbers were 10 bits, but 0 to 31 is only 5 bits. In unsigned sign extension is not necessary. How are you generating the test vectors for the test bench?

[Altera_Forum]

There are two unsigned inputs, a0-a4 and b0-b4. These are converted to signed using the twos compliment number system and multiplied to give a 10 bit output. The output is clocked into a 10 bit d-type flip flop array. The unsigned inputs are then changed to a different number, repeating the process above another two times with different d-type flip flop arrays. This gives three 10 bit outputs, which then need to be added together. (This is for a matrix multiplier). I need the sign extension as the circuit needs to be able to accept both signed and unsigned numbers.  

 I'm using the count function to generate the test vectors. The problem I'm getting looks like this. When testing, (511+255+127 = 893). That's absolutely fine, working no problem. As soon as a negative number is included, the problem arises. Example from testing, (-512+256+128 = 896). Obviously this should be displaying an answer of -128! I've tried around 40 different combinations of adders and keep hitting the same issue...

[Altera_Forum]

How big is your signed output (how many bits) after the adder? Adding three 10-bit numbers requires 12 bits for the result. 

 For what it's worth this would be SO much easier in verilog.

[Altera_Forum]

I have a 12 bit output, this is why I don't understand the issue! And unfortunately I have only been taught to use Block Diagrams. (I use the term taught loosely, more like self taught). I'd love to learn verilog but I simply don't have the time :(

[Altera_Forum]

As 10-bit hex numbers 896 and -128 are identical (0x380). But as 12-bit hex numbers 896 = 0x380 and -128 = 0xF80. Are you sure your output is signed and 12 bits? What do you get if you add 511 + 511 + 511? How about -1 + -1 + -1? And how about -512 + 0 + 0? 

 Play with different numbers and the problem should eventually become obvious.

[Altera_Forum]

I've been playing around as suggested, and it looks like the answers come out incorrectly when the 9th and 11th bits are high, so it looks like the issue is centered around them.