Adding SV interface to PD _hw.tcl

[hbl]

Trying to define a SV interface in PlatformDesigner _hw.tcl file but I keep getting error message about port/interface! The SV interface declaration was loaded using:

add_fileset_file system_bus_if.sv SYSTEM_VERILOG PATH system_bus_if.sv SYSTEMVERILOG_INTERFACE

I've added the following to the _hw.tcl file

add_sv_interface bus_if system_bus_if

set_port_property data SV_INTERFACE_SIGNAL bus_if

This triggered a "No port data" error. Then I added

add_sv_interface bus_if system_bus_if

add_interface_port bus_if data data Input 8

set_port_property data SV_INTERFACE_SIGNAL bus_if

which triggered an "interface bus_if does not exist" error.

What's the correct syntax to declare SV interface in PD _hw.tcl file?

Thanks

[sstrell]

Did you follow this: https://www.intel.com/content/www/us/en/docs/programmable/683609/23-3/declaring-systemverilog-interfaces-in-hw-tcl.html

The signal should be readdata or writedata, not just "data", but make sure you follow the rest of the example in the user guide.

Also, I presume you are using Pro, not Standard.

[hbl]

Yes. This example (the only one we can find on Intel website) is very confusing; there are two interfaces (one avalon_slave and one SV interface) that have the exact same signal names! Adding just the SV interface part doesn't work (we keep getting the errors mentioned in my original post). We tried so many different combinations but nothing worked!

My question is quite simple. What is the procedure to follow to define an SV interface in PD _hw.tcl file. For example:

1. add_sv_interface bus_if system_bus_if

2. set_sv_interface_property bus_if USE_ALL_PORTS True

... (what's missing here?)

4. set_port_property data SV_INTERFACE_SIGNAL bus_if

[sstrell]

Did you try "readdata" or "writedata" instead of just "data"?  If you have no ports defined correctly in the interface, that might explain why you get the interface does not exist error.  There has to be at least one signal/port in an interface.

[hbl]

Not sure what you are referring to. The bus_if signal (not port) is called data (see below). How's this going to affect the SV definition?

interface bus_if

logic [7:0] data;

endinterface

[sstrell]

You have to use the standard signal names to define signal roles in an interface for a custom component.  A SystemVerilog interface is not exactly the same as a Platform Designer interface.  In the example, it shows 4 signals: address, write, writedata, and readdata.  These match the names that must be used for Avalon.  You can use different names in your code but then there must be a mapping to the correct signal roles for the Platform Designer interface using SV_INTERFACE_SIGNAL to add the signals to the interface and SV_INTERFACE_SIGNAL_NAME to do the name mapping: https://www.intel.com/content/www/us/en/docs/programmable/683609/23-3/port-properties-38884.html.  With a SV interface, you can use the USE_ALL_PORTS property, but then the signal names in your SV interface must exactly match the signal roles defined in the spec: https://www.intel.com/content/www/us/en/docs/programmable/683091/22-3/memory-mapped-interface-signal-roles.html

I don’t know why USE_ALL_PORTS is in that example if the ports are then defined right there, but here’s the page describing USE_ALL_PORTS: https://www.intel.com/content/www/us/en/docs/programmable/683609/23-3/systemverilog-interface-properties.html

So the short and easiest answer is if your signal names in your SV interface match the required signal role names in the Avalon spec, you can just use USE_ALL_PORTS to set up the interface.

[hbl]

I think the SV interface support in PD that doesn't make any sense at all. For example, the "system verilog interface" option in PD is absolutely useless (cannot be edited in the GUI and if set in the _hw.tcl it doesn't show up in the GUI).

Using USE_ALL_PORTS by itself doesn't work unless, I think, the port is added to the PD module somehow (can't figure out that one yet, I tried "add_interface_port bus_if data but" it didn't work due to undefined bus_if interface). If that's the case, might as well add the individual signal separately to the top module.

Anyway, I think I wasted enough time on this useless option. Conclusion, unless someone can demonstrate a working example, SV interfaces are not supported in Platform Designer (Quartus Prime Pro).

[Nurina]

Hi,

Are you able to share the .qar file of your project so that I can work on it?

To generate this, go to Project>Archive Project.

Regards,

Nurina

[Nurina]

Also, you may find this thread useful: https://community.intel.com/t5/Intel-Quartus-Prime-Software/Failed-to-create-SystemVerilog-interface-in-hw-tcl-in-Platform/m-p/1523222

Regards,

Nurina

[Nurina]

Hi,

Any updates?

Regards,

Nurina

[Nurina]

Hi,

We have not received a reply from you. As such, I now transition this thread to community support. If you have a new question, Feel free to open a new thread or login to ‘ https://supporttickets.intel.com ’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

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Best regards,

Nurina