Agilex 3 GTS PCIe IP missing

[GabrielC]

I plan a new design using PCIe 3 and LPDDR4 using Agilex3.
I already have a prototype project using an existing Cyclone 5 board, and it worked just fine.
I tried to move to Agilex3 (Quartus Prime Pro 25.1.1), but the IP is completely different.

My logic was designed with Avalon MM components, and for Cyclone 5 the IP was handling all TLP bridging to MM, and even had a tx channel for bus mastering (I used msgdma).

But I could not find anything similar for Agilex 3...

There is a PIO design example; even if it works, I also need tx bus mastering.

Do I have to handle all TLP myself?? I don't have the experience for this, might not be realistic...

Disabling the device compatibility, I see a lot for potential IP... e.g. GTS AXI Multichannel DMA, why is it just for Agilex 5?

I see online SSGDMA IP DMA PCIe... also only for Agilex 5??

Why this limitation?

Thanks,
Gabrile

[GabrielC]

Hi Wincent,

I wrote explicitly... MCDMA (alone!, no user logic) does NOT fit even with minimum settings (PCI 128Bytes, 1 DMA channel).

And you also mention that SGDMA is discontinued...

My only solution right now is to use MCDMA without DMA

That is, just bursting master and slave together with mSGDMA based logic.

This fits into smaller devices... but I have to do low level control to mSGDMA, VFIO... no way to use the MCDMA software/library...

Maybe one day the IP will be improved (to offer reduced memory footprint), but that will probably be too late for me, I need to start the design NOW.

Regards,
Gabriel

[Wincent_Altera]

Hi @GabrielC ,

I will definitely feedback this to our Marketing team to have MCDMA that fits into the smaller device.
Again, please accept my apology for the inconvenience cause to you. And really appreciate for your feedback.

If you happen to have any issue on designing your design, please do file a forum thread or contact your local distributor to file an service ticket. We will be there to ensure your success.

Regards,
Wincent