Hi Intel Community,
I’m studying the R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide and considering purchase of the Agilex™ 7 FPGA I-Series Development Kit (2× R-Tile, 1× F-Tile).
My research goal is to bypass the hardened PCIe/CXL controller and expose the PIPE 5.x SerDes interface into the FPGA fabric, so that I can run a custom soft controller (own LTSSM, EQ, DLLP/TLP, later extend to CXL.io → CXL.mem with 64B FLITs). Before purchasing, I’d like to confirm:
PIPE Direct availability
Does the I-Series Dev Kit expose R-Tile PIPE Direct to the fabric (via EMIB), enabling a full soft PCIe/CXL controller?
Any board-level constraints (e.g., octet-wide Gen5 base mode, per-lane Rate2:0/Powerdown1:0 controls)?
Tool/flow support
The User Guide notes that Quartus Pro 21.2 had no example/testbench for PIPE Direct. What is the current Quartus Pro version recommended?
Are there any reference stubs or app notes for PIPE Direct (Tx/Rx wrapper, reset/clocking examples)?
Root Port / Endpoint configs
Any guidance on PERST#, equalization sequencing, retrain, refclk selection when not using the hardened controller?
CXL hybrid approach
If I start with CXL.io only, is it possible to use the hardened PCIe IP just for link/LTSSM while running custom DLL/TLP/CXL layers in soft logic? Or does any custom higher-layer implementation require going fully PIPE Direct?
Board I/O
Which ports (x16 edge connector, MCIO/SFF-TA-1016) are usable in PIPE Direct mode? Any pinout or kit-specific notes?
specifically: if I connect through the edge connector (to a host system), can I still operate the R-Tile in PIPE Direct mode with my soft controller, or is PIPE Direct limited to MCIO breakout only?
Validation environment (important)
I have access to a CXL-capable host (Sapphire Rapids) but no PCIe/CXL protocol analyzer.
Is it realistic to debug link training and equalization in PIPE Direct without an analyzer? If yes, what tools/flows are recommended (ILA debug, Quartus monitors, logging)?
Would you recommend starting with two Agilex kits back-to-back instead of host-only, given that I don’t have an analyzer?
Are there any Intel or third-party reference setups for early CXL bring-up without protocol analyzers?
I’d greatly appreciate any application notes, example projects, TCL scripts, or checklists to help with PIPE Direct bring-up.
Thanks in advance!
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Hi Rong,
Thanks for the detailed reply.
I need to double-check one critical point because Intel docs seem to suggest something different:
- The R-Tile Avalon-ST IP user guide states that in PIPE Direct mode “either one or both of the PCIe and CXL controller stacks are bypassed and the PIPE SerDes interface is exported across EMIB to the FPGA fabric,” which “allows you to implement your own custom controllers in soft IP.” The page notes that in 23.3 there was no design example/testbench generation, but does not say the mode is simulation-only.
The hardware/software requirements section also lists the Agilex 7 I-Series Dev Kit for design example simulation and hardware tests (wording implies on-board hardware is supported).
Product pages for AGI027 (I-Series, 2×R-Tile + 1×F-Tile) and AGM039 (M-Series HBM2e, includes R-Tile) explicitly position these kits for PCIe 5.0/CXL work; the M-series kit requires an MCIO cable.
Given your note that “PIPE mode is for simulation only,” could you please clarify the exact status for Quartus Pro 25.1.1?
Is PIPE Direct mode hardware-usable in 25.1.1, i.e., can we connect the R-Tile PIPE interface across EMIB to user logic and run a soft PCIe or CXL.io controller in the FPGA fabric on real boards (AGI027/AGM039)? Or is it strictly simulation-only at this time?
If hardware is supported, what is the validated flow today?
Any required IP revisions/constraints beyond “whole-octet Gen5 base mode; per-lane Rate[2:0] and Powerdown[1:0]”?
Which dev kit(s) and example/bring-up materials should we use (even if minimal)? The 23.3 note said “no design example generation”; is there any change in 25.1.1?
If it is not hardware-usable yet, is there a planned release where PIPE Direct on R-Tile will be enabled for hardware bring-up, and will AGI027/AGM039 be the supported platforms?
For CXL, I understand it’s a separate IP (license + NDA user guide). Under NDA, is there any minimal top-level showing how to expose the R-Tile PIPE interface to user logic (even without a full design example), or is the CXL Base HIP currently the only production-supported path for CXL on R-Tile?
Lastly, thanks for confirming the software-driven LTSSM checking; we’ll proceed without a protocol analyzer per your guidance. If PIPE Direct hardware is supported, can that same software monitor LTSSM while our soft controller drives PIPE?
My goal is simple: if PIPE Direct is hardware-usable in 25.1.1, I’ll proceed to prototype a soft PCIe/CXL.io controller on AGI027 (and AGM039 with an MCIO cable); if it’s simulation-only, I’ll adjust plans and stick to the CXL Base HIP path.
Appreciate your clarification!
Best regards,
Yeongmin
