Altera Cyclone V SoC FPGA Development Kit GPIO chip numbering

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I am using an Altera Cyclone V SoC FPGA Development Kit, running a linux-socfpga-4.1.22-ltsi-rt kernel configured (DTB) using the socfpga_cyclone5_socdk.dtsi 

Within the (inherited) socfpga.dtsi I observe the following configuration for the GPIO Bank 0-2:    gpio0: gpio@ff708000 {  # address-cells = <1>;  # size-cells = <0>;  compatible = "snps,dw-apb-gpio";  reg = <0xff708000 0x1000>;  clocks = <&l4_mp_clk>;  status = "disabled";   porta: gpio-controller@0 {  compatible = "snps,dw-apb-gpio-port";  gpio-controller;  # gpio-cells = <2>;  snps,nr-gpios = <29>;  reg = <0>;  interrupt-controller;  # interrupt-cells = <2>;  interrupts = <0 164 4>;  };  };   gpio1: gpio@ff709000 {[/B][/B]  # address-cells = <1>;[/B][/B]  # size-cells = <0>;[/B][/B]  compatible = "snps,dw-apb-gpio";[/B][/B]  reg = <0xff709000 0x1000>;[/B][/B]  clocks = <&l4_mp_clk>;[/B][/B]  status = "disabled";[/B][/B]   portb: gpio-controller@0 {[/B][/B]  compatible = "snps,dw-apb-gpio-port";[/B][/B]  gpio-controller;[/B][/B]  # gpio-cells = <2>;[/B][/B]  snps,nr-gpios = <29>;[/B][/B]  reg = <0>;[/B][/B]  interrupt-controller;[/B][/B]  # interrupt-cells = <2>;[/B][/B]  interrupts = <0 165 4>;[/B][/B]  };[/B][/B]  };[/B][/B]   gpio2: gpio@ff70a000 {[/B][/B]  # address-cells = <1>;[/B][/B]  # size-cells = <0>;[/B][/B]  compatible = "snps,dw-apb-gpio";[/B][/B]  reg = <0xff70a000 0x1000>;[/B][/B]  clocks = <&l4_mp_clk>;[/B][/B]  status = "disabled";[/B][/B] [/B][/B]  portc: gpio-controller@0 {[/B][/B]  compatible = "snps,dw-apb-gpio-port";[/B][/B]  gpio-controller;[/B][/B]  # gpio-cells = <2>;[/B][/B]  snps,nr-gpios = <27>;[/B][/B]  reg = <0>;[/B][/B]  interrupt-controller;[/B][/B]  # interrupt-cells = <2>;[/B][/B]  interrupts = <0 166 4>;[/B][/B]  };[/B][/B]  }; [/B][/B] I then observe this being resolved (runtime, on the board) as: # ls -l /sys/class/gpio[/B][/B] total 0[/B][/B] --w------- 1 root root 4096 jan 1 00:21 export[/B][/B] lrwxrwxrwx 1 root root 0 jan 1 00:21 gpiochip427 -> ../../devices/platform/soc/ff70a000.gpio/gpio/gpiochip427[/B][/B][/B][/B] lrwxrwxrwx 1 root root 0 jan 1 00:21 gpiochip454 -> ../../devices/platform/soc/ff709000.gpio/gpio/gpiochip454[/B][/B][/B][/B] lrwxrwxrwx 1 root root 0 jan 1 00:21 gpiochip483 -> ../../devices/platform/soc/ff708000.gpio/gpio/gpiochip483[/B][/B][/B][/B] --w------- 1 root root 4096 jan 1 00:21 unexport[/B][/B]  [/B][/B]I understand that the numbers 427, 454, 483 are the first GPIO Number of the various GPIO Banks, such that e.g. GPIO Bank# 1 represents GPIO Numbers 454 --> (454 + 28). However, it is not obvious to me *where* these magic numbers (i.e. 427, 454, 483) come from. Can someone explain?  Thanks.