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Altera_Forum
Honored Contributor I
1,127 Views

How to enable SDRAM ECC in the Qsys

Hi, 

How can I enable SDRAM ECC in the Qsys? 

Best Regards
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4 Replies
Altera_Forum
Honored Contributor I
29 Views

I assume you are talking about the HPS SDRAM (which is different from the FPGA SDRAM). For HPS SDRAM, navigate to the HPS Qsys Component --> SDRAM tab --> Memory Parameters 

 

If you are using 32-bit interface width, put the number "40" here. In the Qsys Message box, you should see the note:  

Info: soc_system.hps_0: ECC will be enabled in the preloader because an interface width of 24 or 40 has been chosen.
Altera_Forum
Honored Contributor I
29 Views

Hi, 

Many thanks. Can I used this way for DE0-Nano-SOC board? 

Best Regards
Altera_Forum
Honored Contributor I
29 Views

I select interface width 40. Should I use interface width 24 for DE0-Nano-SOC board?

Altera_Forum
Honored Contributor I
29 Views

It looks like DE0-Nano-SoC only has 32 DQ pins - thus I think you can't use interface width of 40. You can try using 24 and see if it is working.