Altera CycloneIII FPGA PLL problem

[Altera_Forum]

The PLL input clock is 27M. It is multipied and output a clock of 270M to supply the ASI IP core. 8 PCB boards are in test and downloaded the same FPGA program. The problem is, 4 out of 8 boards can access the process with a correct PLL output 270M clock, while 4 fo them cannot. In the faulty ones, it shows "waiting for clock" or a quite mess wave when you use the faulty output clock as the signaltap sampling clock. If you draw the faulty output clock to a pin, the wave amplitude is much smaller than the right ones. Can I define the problem is on PLL?  

 If yes, why there are 4 boards correct?? How I can solve it? Thanks a lot!

[Altera_Forum]

Route the input clock to an output pin and check it. If this looks bad, check the solder joints of your clock signal on the board.  

Bad joints will introduce reflections and spikes and that makes the PLL to misbehave.  BTW are the faulty PLLs in lock?  -- Ton

[Altera_Forum]

Thank you for your reply,dear std_logic_vector! 

I have routed the input clock to an output pin and checked it.27M,the output clock is all right.So I think the problem isnot bad joints.   The locked signal in faulty PCB is low,but the locked signal in PCB that can works well is also low.It is very strange.

[Altera_Forum]

Ok, input clock is good, solder joint are good. 

Are all devices under test of the same speed? Are the PLL power supplies ok (Vcca and Vccd)? Voltage? Decoupling? Grounding?  That's all I can think of.  Try some other input- and/or output-frequencies. Does the problem remain?  -- Ton

[Altera_Forum]

Check whether you are exceeding the VCO frequency range anytime between input to output.