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CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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Selection of CPLD speed grade

Altera_Forum
Honored Contributor II
‎08-19-2010 02:15 AM
1,127 Views

Hi, 

 

How to come to a conclusion that speed grade of the CPLD selected for a particular design running at 50 Mhz is OK??
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Altera_Forum
Honored Contributor II
‎08-19-2010 02:40 AM
334 Views

You need to perform static timing analysis. In addition to that, you can also use gate level simulations. 

 

Quartus has two timing analysis tools: the Classical TA and the TimeQuest TA. 

TimeQuest is the preferred option, but it does not support old devices. 

If you're using older devices, such as MAX 3000/7000 CPLDs will have to stick with the Classical TA.
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