Altera MAXSONAR LVEZ1 sensor

[Altera_Forum]

Hi 

 I want to cnnect the LVEZ1 sensor to the de2 board. I have read that the sensor has a serial rs232 format output. But i am not sure how i can connect these to the rs232 module on the de2 board. I am aware of the pin configuration and i only wish to receive data. Can i connect them directly "Altera FPGA families do not comply with RS-232 voltage levels, and may be damaged if driven directly by signals from an RS-232 connector"? Even after connect how do i actually read the data and use it in my Verlilog?  Thanks for any help

[Altera_Forum]

Hi, 

the RS-232 interface is defined as +/-6V to +/-12V for logic "0" and "1". Thus these voltages (being negative and far more than the I/O voltages the FPGA can deal with) cannot be connected w/o RS-232 to logic level converters like the MAX232 or similar devices.  It might be a "workaroung" (in case the sensor can send data w/o being configured, as I assume for you wrote "I only wish to receive data") that you connect the TxD line (transmit data) from the sensor via a serial resistor and a zener diode at the FPGA pin (referenced to FPGA GND) to ensure the level does not exceed the I/O voltage and that it does not fall below max. negative of the FPGA I/O voltage (for this a schottky diode in parallel to the zener diode would be recommended).  In fact, after configuration turning the clamping diode in the I/O structure would eliminate the zenerdiode (not the serial resistor and the shottky to GND), but for that the sensor may not operate prior the FPGA has configured (unconfigured / during configuration the clamping diode is not active!) I would first check this resistor/diode network for matching level rather connecting it directly to the FPGA. If the transmission rate is too high, the capacitance of the zener diode may cause timing issues as the signal at the FPGA rises too slow - one more thing to check for. To be honest - comparing costs for resistance, zenerdiode and shottky by a simple RS-232 to logic converter... It might not be worth the effort. And - the converter IC allows you to send data as well (you don't want to - now...)  If this is not a serial production design requiring optimization to the last "tenth of a cent", I would recommend using the converter...  Best regards :-)

[Altera_Forum]

How else could i do this ... i need the readings in my verilog module thats all. Any other way? Is there a way to provide the serial data from an arduino because that can easily do a analog read? How do i do it using a converter? Do I have to purchase a ADC module?

[Altera_Forum]

Hi, 

this is a two step process.. First you have to ensure the signals from the sensor can be connected to the FPGA, second is to write the verilog module "decoding" the information sent by the sensor. I'm not familar with the sensor, but if the sensor has a RS-232 compliant interface, this first defines the physical interface (level, timing, ...) and the coding of the data as serial datastream... Thus, having the signals connected to the FPGA you need something like an UART or you have to implement the decoding of the serial datastream by yourself (it's no rocketscience - see RS-232 defintion e.g. at wikipedia)... I did some RS-232 interface already but I'm programming in VHDL... There is another thread (if I recall) dealing with (same?) sensor, stating the signals are coded as defined by RS-232 but not +/- voltage. If those are 0 to VCC, the sensor can be connected directly to the FPGA - but this needs to be checked first. Regards...

[Altera_Forum]

http://electronics.stackexchange.com/questions/22180/de2-board-reading-sensor-reading 

 From the TX explanation it looks like its from 0 to Vcc. So to implement this I just have to read the UART tutorial?  http://www.fpga4fun.com/serialinterface4.html Can i use the code mentioned in that website?

[Altera_Forum]

Also can i directly connect the sensor to the de2 : range is 2.2 to 5 V. Sensor : TX, Vcc, GND -> DE2 : RX, DTR, GND (2, 4, 5) directly?

[Altera_Forum]

Hi there, 

according to the link you sent, the sensor has RS-232 dataformat with 0 to VCC physical levels (thus violating the full RS-232 specification). In fact this allows direct connection to the DE2, just ensure to use the I/O voltage as supply voltage for the sensor to match levels... In fact you just have to look to the UART tutorial / the description at fgpa4fun.com seems to be ok as well. As an option you could use the PWM output at PW as described in the first link (I would generate e.g. a 14.7us clock signal and count the pulses per pulse of the sensor. The result would be the distance in 0.1inch... (use 1.47us clock for 1/100 inch resolution....).  HTH

[Altera_Forum]

Thanks. 

 Should I be using the Nios ii altera's software for this purpose or just have a module function uart and call this function whenever i need to receive data? And also how do i use the I/O voltage as supply? Are the connections I mentioned earlier from sensor to rs232 (de2) look right?

[Altera_Forum]

Hi, 

sorry for causing irritations... The ALTERA FPGA may be operated e.g. with 2.5V or 3.3V I/O supply - thus you have to ensure that the sensor and the FPGA use identical voltages. With this in mind, you should be fine with connection Supply, GND and TxD from Sensor to RxD of DE2.  For the sensor sending data w/o being interrogated (otherwise you would have to implement "Send" as well on the FPGA), I assume the best is instantiation of a module continuously receiving and converting the datastream generated by the sensor and providing the result via the module's interface to the rest of your code. As I'm not familar with Verilog - this is like I would solve this in VHDL...

[Altera_Forum]

thats really helpful ty ... so i m going ahead making the above connections and using the code http://www.fpga4fun.com/serialinterface4.html here just the receiver module nothing else. Will let you know if it works.

[Altera_Forum]

--- Quote Start ---  module test_rs232(input CLOCK_50, output [17:0] LEDR, output UART_TXD, input UART_RXD, input [1:0] KEY);    wire reset;  assign reset = ~KEY[0];    parameter DATA_WIDTH = 8;  wire [DATA_WIDTH-1:0] received_data;  wire [DATA_WIDTH-1:0] transmit_data;  wire transmitting_data;  wire receiving_data, data_received;  wire transmit_data_en;   RS232_In u3(.clk(CLOCK_50), .reset(reset), .serial_data_in(UART_RXD), .receive_data_en(1'b1), .received_data(received_data),   .data_received(data_received), .receiving_data(receiving_data));    assign LEDR[7:0] = received_data; endmodule  //RS232_In.v  module RS232_In ( // Inputs input clk, input reset, input serial_data_in, input receive_data_en, // Outputs output reg [(DATA_WIDTH-1):0] received_data, output reg receiving_data, output reg data_received, output baud_clock );  parameter BAUD_COUNT = 9'd434; parameter DATA_WIDTH = 8; parameter TOTAL_DATA_WIDTH = DATA_WIDTH + 2;  wire shift_data_reg_en; wire all_bits_received;   assign baud_clock = shift_data_reg_en; reg [(TOTAL_DATA_WIDTH - 1):0] data_in_shift_reg; //reg receiving_data; reg prev_receiving_data;    always @(posedge clk) begin  if (reset == 1'b1)  receiving_data <= 1'b0;  else if (all_bits_received == 1'b1)  receiving_data <= 1'b0;  else if (serial_data_in == 1'b0)  receiving_data <= 1'b1; end  always @(posedge clk) begin  prev_receiving_data <= receiving_data;  if (receiving_data==1'b1)  data_received <= 1'b0;  else if (prev_receiving_data==1'b1)  begin  data_received <= 1'b1;  received_data <= data_in_shift_reg[DATA_WIDTH:1];  end end  always @(posedge clk) begin  if (reset == 1'b1)  data_in_shift_reg <= {TOTAL_DATA_WIDTH{1'b0}};  else if (shift_data_reg_en)  data_in_shift_reg <=   {serial_data_in, data_in_shift_reg[(TOTAL_DATA_WIDTH - 1):1]}; end  Baud_Counter RS232_In_Counter ( // Inputs .clk(clk), .reset(reset), .reset_counters(~receiving_data), // Outputs .baud_clock_rising_edge(), .baud_clock_falling_edge(shift_data_reg_en), .all_bits_transmitted(all_bits_received) ); defparam   RS232_In_Counter.BAUD_COUNT= BAUD_COUNT,  RS232_In_Counter.DATA_WIDTH= DATA_WIDTH; /* Altera_UP_SYNC_FIFO RS232_In_FIFO (  // Inputs  .clk (clk),  .reset (reset),   .write_en (all_bits_received & ~fifo_is_full),  .write_data (data_in_shift_reg[(DATA_WIDTH + 1):1]),   .read_en (receive_data_en & ~fifo_is_empty),    // Bidirectionals   // Outputs  .fifo_is_empty (fifo_is_empty),  .fifo_is_full (fifo_is_full),  .words_used (fifo_used),   .read_data (received_data) ); defparam   RS232_In_FIFO.DATA_WIDTH = DATA_WIDTH,  RS232_In_FIFO.DATA_DEPTH = 128,  RS232_In_FIFO.ADDR_WIDTH = 7; */ endmodule  module Baud_Counter (input clk, input reset, input reset_counters, output reg baud_clock_rising_edge, output reg baud_clock_falling_edge,   output reg all_bits_transmitted);  parameter BAUD_COUNTER_WIDTH = 9; parameter BAUD_COUNT = 5; parameter BAUD_TICK_COUNT = BAUD_COUNT - 1; //9'd433; parameter HALF_BAUD_TICK_COUNT = BAUD_COUNT / 2; //9'd216;  parameter DATA_WIDTH = 9; parameter TOTAL_DATA_WIDTH = DATA_WIDTH + 2;  reg [(BAUD_COUNTER_WIDTH - 1):0] baud_counter; reg [3:0] bit_counter;  // control baud_counter always @(posedge clk) begin  if (reset == 1'b1)  baud_counter <= {BAUD_COUNTER_WIDTH{1'b0}};  else if (reset_counters)  baud_counter <= {BAUD_COUNTER_WIDTH{1'b0}};  else if (baud_counter == BAUD_TICK_COUNT)  baud_counter <= {BAUD_COUNTER_WIDTH{1'b0}};  else  baud_counter <= baud_counter + 1'b1; end  // control baud_clock_rising_edge signal always @(posedge clk) begin  if (reset == 1'b1)  baud_clock_rising_edge <= 1'b0;  else if (baud_counter == BAUD_TICK_COUNT)  baud_clock_rising_edge <= 1'b1;  else  baud_clock_rising_edge <= 1'b0; end  // control baud_clock_falling_edge signal always @(posedge clk) begin  if (reset == 1'b1)  baud_clock_falling_edge <= 1'b0;  else if (baud_counter == HALF_BAUD_TICK_COUNT)  baud_clock_falling_edge <= 1'b1;  else  baud_clock_falling_edge <= 1'b0; end  // control bit counter always @(posedge clk) begin  if (reset == 1'b1)  bit_counter <= 4'h0;  else if (reset_counters)  bit_counter <= 4'h0;  else if (bit_counter == TOTAL_DATA_WIDTH)  bit_counter <= 4'h0;  else if (baud_counter == BAUD_TICK_COUNT)  bit_counter <= bit_counter + 4'h1; end  // control all_bits_transmitted signal always @(posedge clk) begin  if (reset == 1'b1)  all_bits_transmitted <= 1'b0;  else if (bit_counter == TOTAL_DATA_WIDTH)  all_bits_transmitted <= 1'b1;  else  all_bits_transmitted <= 1'b0; end  endmodule   --- Quote End ---    The code compiles but there is no ledr's turned on.  The code is from here http://www.johnloomis.org/digitallab/rs232/rs232lab.qdoc.html#baud_counter.v  http://imageshack.us/photo/my-images/528/img00276201111141211.jpg/  Please let me knoe if u guys see any problem

[Altera_Forum]

r3f3ctionz : have u done ur project using ultrasonic ez1? can u help me??

[Altera_Forum]

hi, actually i'm using the same sensor now for my project. how did you manage to interface the sensor to de2 board? tq