Altera Monitor Program upload Error

[Altera_Forum]

I have downloaded the Altera Monitor Program for use with the DE-0 board. I am able to start it and upload the computer design. I have been able to write verilog in Quartus and upload designs. However when I try and upload a program via Monitor, I get the error box shown in the attached file. 

 When looking at the Info & Errors window I get this  C:/altera/13.1/quartus/bin/quartus_pgm -c "USB-Blaster [USB-0]" --auto 1) USB-Blaster [USB-0]  020F20DD EP3C16/EP4CE15 C:/altera/13.1/quartus/bin/quartus_pgm -c "USB-Blaster [USB-0]" -m jtag -o P\;"C:/altera/13.1/University_Program/Computer_Systems/DE0/DE0_Basic_Computer/verilog/DE0_Basic_Computer.sof"@1 Info: ******************************************************************* Info: Running Quartus II 32-bit Programmer  Info: Version 13.1.0 Build 162 10/23/2013 SJ Web Edition  Info: Copyright (C) 1991-2013 Altera Corporation. All rights reserved.  Info: Your use of Altera Corporation's design tools, logic functions   Info: and other software and tools, and its AMPP partner logic   Info: functions, and any output files from any of the foregoing   Info: (including device programming or simulation files), and any   Info: associated documentation or information are expressly subject   Info: to the terms and conditions of the Altera Program License   Info: Subscription Agreement, Altera MegaCore Function License   Info: Agreement, or other applicable license agreement, including,   Info: without limitation, that your use is for the sole purpose of   Info: programming logic devices manufactured by Altera and sold by   Info: Altera or its authorized distributors. Please refer to the   Info: applicable agreement for further details.  Info: Processing started: Tue Feb 09 09:21:09 2016 Info: Command: quartus_pgm -c "USB-Blaster [USB-0]" -m jtag -o P;C:/altera/13.1/University_Program/Computer_Systems/DE0/DE0_Basic_Computer/verilog/DE0_Basic_Computer.sof@1 Info (213045): Using programming cable "USB-Blaster [USB-0]" Info (213011): Using programming file C:/altera/13.1/University_Program/Computer_Systems/DE0/DE0_Basic_Computer/verilog/DE0_Basic_Computer.sof with checksum 0x00364108 for device EP3C16F484@1 Info (209060): Started Programmer operation at Tue Feb 09 09:21:10 2016 Info (209016): Configuring device index 1 Info (209017): Device 1 contains JTAG ID code 0x020F20DD Info (209007): Configuration succeeded -- 1 device(s) configured Info (209011): Successfully performed operation(s) Info (209061): Ended Programmer operation at Tue Feb 09 09:21:11 2016 Info: Quartus II 32-bit Programmer was successful. 0 errors, 0 warnings  Info: Peak virtual memory: 192 megabytes  Info: Processing ended: Tue Feb 09 09:21:11 2016  Info: Elapsed time: 00:00:02  Info: Total CPU time (on all processors): 00:00:01 nios2-elf-gcc -g -O1 -ffunction-sections -fverbose-asm -fno-inline -mno-cache-volatile -mhw-mul -mno-hw-div -I"C:/altera/13.1/nios2eds/components/altera_nios2/HAL/inc" -DSYSTEM_BUS_WIDTH=32 -DALT_SINGLE_THREADED -D_JTAG_UART_BASE=268439552 -Wl,--defsym -Wl,nasys_stack_top=0x800000 -Wl,--defsym -Wl,nasys_program_mem=0x0 -Wl,--defsym -Wl,nasys_data_mem=0x0 -Wl,--section-start -Wl,.exceptions=0x20 -Wl,--section-start -Wl,.reset=0x0 -Wl,--script="C:/altera/13.1/University_Program/Monitor_Program/build/nios_cpp_build.ld" -o "C:/731_S16/NiosIIStart/getting_started.elf" "C:/731_S16/NiosIIStart/getting_started.c" "C:/altera/13.1/University_Program/Monitor_Program/lib/jtag_uart.c"  ELF generated at C:/731_S16/NiosIIStart/getting_started.elf. nios2-elf-objcopy -O srec "C:/731_S16/NiosIIStart/getting_started.elf" "C:/731_S16/NiosIIStart/getting_started.srec"  SREC generated at C:/731_S16/NiosIIStart/getting_started.srec.  Which doesn't say anything about an upload error.  I am on Windows 8.1 and I have tried to update all instances of cygwin.  Any ideas?  Doc Day Kansas State University. Any ideas