Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

Discussions

Post a question

Twister

by on Latest post on by

2 Replies 2171 Views

2171

Posting IP

by on

0 Replies 1917 Views

1917

Popular Discussions

FPGA passive serial configuration -- detect as PCIe device in Linux after configuration

1 27

MAX V Exposed pad solder reflow problem

0 10

Converting Oscillator HCSL Output to SSTL_18

0 10

Top kudoed authors

Epsum factorial non deposit quid pro quo hic escorol.

User

Count

Re: SSH connection lost - Cannot copy executable file into de10-nano

Re: MAX V Exposed pad solder reflow problem

Re: The rx_is_lockedtoref in Native PHY cannot be stabilized at 1

MAX10 FPGA design : some questions about clock and other aspects

Re: Enable on-chip termination for Differential Transceiver clocks

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.

Programmable Devices

Discussions

Featured Content