DPA Word Alignment

[Altera_Forum]

I'm working on a Stratix III design using DPA on links between FPGAs on the same board. My question is: is it really necessary to have to dynamically train each channel to achieve word alignment? i.e. can't it just be set statically and assumed to always be in the same alignment? 

 Having monitored the transmitted signals, the clock and data always have the same phase relationship (msb aligned with rising edge of clock) so I don't quite see why I would assume it could be anything different.  At the moment, on the Rx side, my msb seems to be shifted by 3 bit positions but it's always the same as far as I can tell.  I don't really want to have design a complex system of data checking to achieve alignment at start-up, unless I really have to.  P.S. I'm running at about 400Mbps with a SERDES factor of 7.

[Altera_Forum]

I haven't looked at the DPA recently, but 400Mbps data streams isn't overly fast. Source synchronous double-data rate interfaces can do this, and they don't do any sort of oversampling or anything, i.e. it's all static timing analysis to center the clock on the data over PVT. At the really high rates is where this tends to fall apart and you need something that can re-calibrate. Of course, you're probably not going to get anyone to guarantee anything, but you're probably fine. Since it's an FPGA, you can design it the easier way at first and see what happens. It probably depends on how much testing you're going to do, what the application is(i.e. this might not be good for flight controls), and what you feel comfortable with. I've seen a number of designs where the designer just tries all the settings on the input delay chain(64-delays in Stratix II), and figure out how big their window was, then just center on that. If they had margin they were comfortable with, they went with it, and I haven't heard that anything went wrong.

[Altera_Forum]

No, it's not that fast but if I stick with a SERDES/DPA approach I always have the option of pushing things faster later on. 

 What I have discovered is that bit 6 (msb) on the Tx side comes out in bit 3 on the Rx side which happens to be the middle bit of the 7. Can this be explained?  As far as I can tell from the Stratix III documentation this is what should happen Tx clock/data: /^^^^^^^^^\____________/^^^^^^^^\_____________/  <6><5><4><3><2><1><0><6><5><4><3><2><1><0>  Rx data: <...............6543210............><...............6543210............>  I'm getting: Tx clock/data: /^^^^^^^^^\____________/^^^^^^^^\_____________/  <6><5><4><3><2><1><0><6><5><4><3><2><1><0>  Rx data: <................2106543............><................2106543............>

[Altera_Forum]

Agreed, but if you push things faster, than you'll definitely want to align everything at start-up, so it becomes an issue on whether you want to do that now or later on the condition that the speeds do improve. (I briefly looked at the waveform but haven't done enough with this recently to intelligently reply. Maybe someone else can help or you can file an SR.)

[Altera_Forum]

--- Quote Start ---  I'm working on a Stratix III design using DPA on links between FPGAs on the same board. My question is: is it really necessary to have to dynamically train each channel to achieve word alignment? i.e. can't it just be set statically and assumed to always be in the same alignment?  Having monitored the transmitted signals, the clock and data always have the same phase relationship (msb aligned with rising edge of clock) so I don't quite see why I would assume it could be anything different.  --- Quote End ---    It would be easy if there is no external factor that can affect the characteristic of the signals. In real world, this cannot be assumed. Temperature and voltage variations can cause changes to signal's charateristics. Having to train the channels dynamically is the way to go.  Hope this helps.