Boundary-scan testing with Arria GX and Stratix III

[Altera_Forum]

Hi, 

 I would like to implement boundary-scan testing on my new board. I don't understand how we must connect configuration pins (nCONFIG, nSTATUS, CONF_DONE, TRST, MSEL, nCE). Do these signals must be connected as a "normal" application (i.e. nCONFIG, nSTATUS, CONF_DONE to Vcc and nCE to GND + MSEL as required configuration scheme)?  Can anyone help me? Thanks.

[Altera_Forum]

Your question does not make any sense. 

 Boundary Scan testing of the FPGA and surrounding parts will be executed via the JTAG connection to the part.  The pins that you have listed may or may not be used to configure the FPGA. They are non related items.  Please re-read the topics on configuration of the FPGA to better understand the function of loading (configurating) the part.  Then after configuration, if you wish to use the JTAG interface for Boundary Scan, just use the JTAG pins.  I hope this makes sense.

[Altera_Forum]

Thanks. 

It's clear now. However, I read that JTAG standard for TCK is a pull-up. In all Altera schematics, I saw a pull-down. Is this compatible?

[Altera_Forum]

I am not sure what 'compatible' means in this case. 

 If you have read in the official JTAG 1149 standard that it says TCK should be pulled up and in the schematics you see pull downs, then clearly they are different.  I would read several Altera Users Guides and perhaps also look into the pinput report from a design and see if there is any mention on termination in there.  I do know that Altera definately tells you to terminate it and it may just be that Altera has decided that terminating it low works best for their designs?  The information t hat I have received for Stratix II and Stratix II GX (of which Arria GX is a varient) is as follows;  Connect this pin to a 1K Ohm resistor to GND.   Glad to help out.   How about some Reputation points?? (link on the Blue line above one of posts.) Randalls getting close and Brad & Rysc are pulling away...