Programmable Devices

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Programmable Devices

Discussions

Stand-Alone Lightweight IP

Streaming_Ciphers_and_LFSRs

uClinux Distribution Version 1.3

Jester

Nios II floating point custom instructions

SP FPU (32 Bit) - Verilog

DP FPU (64 bit IEEE) (verilog)

Modified http server that parses server-side text

Modified lan91c111 component

Graphic Line Draw

Dallas/Maxim 1-Wire Interface (3 parts)

FPADD/MULT Project NIOSII/F

FPADD FPMULT for NIOS + Cyclone

Twister

Posting IP

Featured Content

FPGA passive serial configuration -- detect as PCIe device in Linux after configuration

Converting Oscillator HCSL Output to SSTL_18

simulation for the HBM2E Interface FPGA IP

Re: The rx_is_lockedtoref in Native PHY cannot be stabilized at 1

Re: Enable on-chip termination for Differential Transceiver clocks

Re: Quartus 18.1 & DE2-115

Re: Quartus programmer start failed

FPGA passive serial configuration -- detect as PCIe device in Linux after configuration