Programmable Devices

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.

Programmable Devices

Discussions

Jester

Nios II floating point custom instructions

SP FPU (32 Bit) - Verilog

DP FPU (64 bit IEEE) (verilog)

Modified http server that parses server-side text

Modified lan91c111 component

Graphic Line Draw

Dallas/Maxim 1-Wire Interface (3 parts)

FPADD/MULT Project NIOSII/F

FPADD FPMULT for NIOS + Cyclone

Twister

Posting IP

Featured Content

FPGA passive serial configuration -- detect as PCIe device in Linux after configuration

simulation for the HBM2E Interface FPGA IP

MAX V Exposed pad solder reflow problem

Re: The rx_is_lockedtoref in Native PHY cannot be stabilized at 1

Re: Enable on-chip termination for Differential Transceiver clocks

Re: Quartus 18.1 & DE2-115

Re: Quartus programmer start failed

The part of EPM7064AETI100-7N is with date code of 2301