Programmable Devices

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Programmable Devices

Discussions

"Power Pair" in Cyclone II

Wide MACCs in Stratix III

does LVDS input clock have internal bias?

changing PLL parameters to get desired PLL Implementation

Simulation of PLL lock time

how to connect unused reserved pins on the board

DCLK frequencies are supported by EPCS?

Altera device VI or IV curves?

PLL Lock range

VCCIO for PLL banks?

RoHS EPCS

In-rush Current

Device seems to go idle randomly

LED drivers in MAXII

Delaying My Clock

Featured Content

Configuration via Protocol (CvP) fail after loading the periphery image

DE1 Cyclone V Verilog

Cyclone 3 Not entering AS Mode

Re: Cyclone 10 LP configuration/JTAG pin VCCIO

To know life cycle status of CPLD parts EPM240T100C4N and EPM240T100I5N

FPGA passive serial configuration -- detect as PCIe device in Linux after configuration

Re: system.h not reloading