Altera emac: Is it TSE or designware?

[rshal2]

Hello,

I am a bit confused with altera emac.

I need to use emac from HPS in arria V or cyclone V.

Checking both TRM documentation of these FPGA, it is described (in each TRM , and also in memory map ), that it use DesignWare emac.

But I then see in Cyclon V devkit documentation:

“Gigabit Ethernet port

RJ-45 connector which provides a 10/100/1000 Ethernet connection via a Micrel KSZ9021RN PHY and the FPGA-based Altera Triple Speed Ethernet MegaCore function in RGMII mode.”

Is it a TSE or DesignWare ?

Thank you!

ran

[Deshi_Intel]

Hi Ran, Arria V or Cyclone V SOC FPGA support 2 different type of EMAC IP. 1) HPS -> Design Ware EMAC IP 2) FPGA core logic -> soft TSE MAC IP If you are interested with using HPS to interact with EMAC, then you should go with DesignWare EMAC. Thanks. Regards, dlim

[rshal2]

Hello Dlim,

Thanks you very much.

But is it possible to use FPGA core TSE MAC and still get the EMAC output from the HPS pins ?

Thanks,

ran

[Deshi_Intel]

Hi Ran, Unfortunately no. Thanks. Regards, dlim

[rshal2]

Hello Dlim,

I hope I may ask still more about this issue please.

I do find there is kernel driver for ARM for TSE.

As you can see it also here:

This is the driver for the Altera Triple-Speed Ethernet (TSE) controllers using the SGDMA and MSGDMA soft DMA IP components. The driver uses the platform bus to obtain component resources. The designs used to test this driver were built for a Cyclone(R) V SOC FPGA board, a Cyclone(R) V FPGA board, and tested with ARM and NIOS processor hosts separately.

you can also find full text here:

https://www.kernel.org/doc/Documentation/networking/altera_tse.txt

I don't understand how TSE was tested from arm.

Isn't it requires bridges in FPGA for both the TSE and SGDMA IP's which both reside in FPGA ?

Thank you very much for the help,

ranran

[Deshi_Intel]

HI Ranran, If you refer to the reference design that I shared with you in another Forum post https://rocketboards.org/foswiki/Projects/AlteraSoCTripleSpeedEthernetDesignExample Looks like HPS ARM processor is able to connect to FPGA core then to TSE IP. However, it's best if you open up the reference design in Quartus and double check on it. Thanks. Regards, dlim

[rshal2]

Hello Dlim,

I hope I can ask one more on this. I haven't yet checked the reference example, I feel like I still miss some background understanding on the subject.

What do you mean by "Looks like HPS ARM processor is able to connect to FPGA core then to TSE IP. " ?

What is the difference between HPS access to FPGA and HPS ARM access TSE IP ?

Is it that the first case means that TSE is already memory mapped to arm, while the second requires a bridge to HPS ?

Another thing, in arria v reference documentation (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/arria-v/av_54012.pdf) I don't see any mention on TSE is the memory address map, so where can I find how to access TSE from ARM in documentation ?

Thanks!

ranran

[Deshi_Intel]

HI Ranran, Yes, I suggest you go through the Arria V reference doc (av_54012.pdf) to get a better understanding of the overall architecture. HPS (hard processor system) = A combination of various harden functional IP blocks that include one ARM processor + many more smaller IP including the designware EMAC HPS is hardwired connected to EMAC IP and then to certain dedicated FPGA HPS IO pins. HPS also has other data connection path that can connect to FPGA core logic via HPS-FPGA bridge. In the FPGA core logic, user can then instantiate different IP block design like TSE IP or NIOS II In short, FPGA provides multiple ways for user to implement TSE solution 1) Use ARM processor in HPS -> EMAC in HPS -> FPGA HPS dedicated IO pins 2) Use ARM processor in HPS -> HPS-FPGA bridge -> TSE IP 3) Ignore ARM processor and HPS, use NIOS II processor -> TSE IP in FPGA core logic directly So, it's really up to you to choose the solution that best suits your application. Thanks. Regards, dlim

[Deshi_Intel]

So, you should get a better idea now that TSE IP wouldn't be memory map to ARM processor in HPS block Only HPS EMAC IP is memory map to HPS ARM processor