I am a bit confused with altera emac.
I need to use emac from HPS in arria V or cyclone V.
Checking both TRM documentation of these FPGA, it is described (in each TRM , and also in memory map ), that it use DesignWare emac.
But I then see in Cyclon V devkit documentation:
“Gigabit Ethernet port
RJ-45 connector which provides a 10/100/1000 Ethernet connection via a Micrel KSZ9021RN PHY and the FPGA-based Altera Triple Speed Ethernet MegaCore function in RGMII mode.”
Is it a TSE or DesignWare ?
I hope I may ask still more about this issue please.
I do find there is kernel driver for ARM for TSE.
As you can see it also here:
This is the driver for the Altera Triple-Speed Ethernet (TSE) controllers using the SGDMA and MSGDMA soft DMA IP components. The driver uses the platform bus to obtain component resources. The designs used to test this driver were built for a Cyclone(R) V SOC FPGA board, a Cyclone(R) V FPGA board, and tested with ARM and NIOS processor hosts separately.
you can also find full text here:
I don't understand how TSE was tested from arm.
Isn't it requires bridges in FPGA for both the TSE and SGDMA IP's which both reside in FPGA ?
Thank you very much for the help,
I hope I can ask one more on this. I haven't yet checked the reference example, I feel like I still miss some background understanding on the subject.
What do you mean by "Looks like HPS ARM processor is able to connect to FPGA core then to TSE IP. " ?
What is the difference between HPS access to FPGA and HPS ARM access TSE IP ?
Is it that the first case means that TSE is already memory mapped to arm, while the second requires a bridge to HPS ?
Another thing, in arria v reference documentation (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/arria-v/av_54012.pdf) I don't see any mention on TSE is the memory address map, so where can I find how to access TSE from ARM in documentation ?