Hi! I work with Altera Cyclone IV.
I have a question about altera floating point megafunctions, for example fp_add_sub or fp_mult.
I can choose output latency in clock cycles, minimum is 7 or 6 respectively if mantissa width is 23 and exponent width is 8.
In Xilinx Spartan 3, in floating point core I can specify output latency as low as zero or one clock cycle in same cases.
The question is why Altera doesn't provide such ability, I mean it is useful to have an output faster, especially if I generate Taylor series or smth like that.
