Hi allI'm wondering whether adding a module or an IP to an FPGA design can change the performance. From what I know, I guess the performance would be changed because different place and route result. If so, how to make sure the function is still working or the performance is good after adding a module. I'm asking this question because I have problems in combining two working projects into one. One working project is triple standard SDI receiver and the other is SGDMA. My purpose is to copy video frame from SDI to DDR3 through SGDMA. Both projects works well separately. However, if I instantiate the top modules of these two projects in another top module as a combined design, the SDI receiver fails to receive HD and 3G SDI signals. (luckily, the SD SDI signals can still be received). I even try to disconnect SDI receiver and SGDMA in order to test the SDI receiver independently and it still fails. I am now having no idea on solving the problem. Any possible suggestions are appreciated.
The problem is that SDI is a continuous stream and SGDMA use bursts for DDR3. Check Altera frame buffer IP core, but think of a mechanism how to make SDI stream to do bursts in packets.
Hi SocratesThank you for your reply. I'll try to use frame buffer IP tomorrow. In fact, I do not understand why a continuous stream and burst transfers cause me this problem. Does a continuous stream lead to a full FIFO in SGDMA and affect the SDI receiver? I'm grateful if you are willing to explain it more. BTW, in my working project of SGDMA, the input video source comes from an Altera test pattern generator IP and is feed to SGDMA. (TPG-->(some avalon-st adapter and DC FIFO)-->SGDMA) I don't see much difference between this working project and the SDI one we discussed. (SDI Rx-->CVI-->(some avalon-st adapter and DC FIFO)-->SGDMA) The video sources are both in Avalon streaming interface. I am also wondering what the difference between these two designs. Sorry for asking you too many questions. I'm just very curious about the reasons. Thanks.
Hi SocratesI just found two unassigned IO pins which should be connected to SDI cable driver IC. After I assign correct IO pins, the combined project works stable. So I move on to write the C program running on NIOS II CPU to control the SGDMA. A new problem occurs which makes SDI receiver reset. If I declare the video frame buffer in "stack" of DDR3, the downloading process of elf file is slow. (about 5 second...)
alt_u8 video_buf __attribute__((section(".ddr3")));I guess this slow process somehow makes SDI receiver reset. (rx_status is 1'b1) So I allocate video frame buffer in "heap" of DDR3 to solve the slow downloading problem and it works. (rx_status which indicates frame locked is 1'b1) Thank you for your help.:)
Two more difficult problems about this implementation were found yesterday... :cry:1). Although the SDI receiver works, I found that the data of video frame in DDR3 are all 0x00, which means nothing is transferred by SGDMA. If the SGDMA transfer is correct, I should see two blocks of data in DDR3. One is an Avalon-ST control packet which indicates the format of coming video such as resolution. The other is an Avalon-ST video packet which contains frame or field data. Now the problem is that I can see correct control packet data in DDR3 but the video packet data in DDR3 are all zero. I'm trying to observe the waveform in Modelsim to make sure there's a valid Avalon-ST video packet as an input of SGDMA. Does any wrong parameter setting cause this problem??? 2). Because SGDMA cannot give me a good result, I try to use Frame Buffer IP as Socrates's suggestion. The FPGA design is as follows: (SDI Rx-->CVI-->Frame Buffer-->DDR3) After I enable the GO bit in the control register of Frame Buffer, the data in DDR3 are changed . (The initial data in DDR3 has been set to zero in my program in order to see the data change) However, the data are not what I expect. (The data should be the YCbYCr data from a color bar test pattern video source) I'm wondering whether I accessed incorrect address in DDR3 so that the data is wrong. The base address in the Frame Buffer setting is 0x00000000. Does this address represent a zero address offset of the first frame buffer in DDR3? Moreover, how to compute the starting address of the second frame buffer and even third frame buffer in DDR3? Thank you. :)
No, base address has nothing to do with the memory offset. The base address is required for Nios to access module registers. Check frame buffer documentation.
--- Quote Start --- (SDI Rx-->CVI-->(some avalon-st adapter and DC FIFO)-->SGDMA) --- Quote End --- Hello, YUFU0511! What are You using as "some avalon-st adapter and DC FIFO" to connect CVI and SGDMA?
Hi AphratonIf I remember right, opening a qsys file and clicking "system" --> "Insert avalon-st adapter" will automatically add some avalon-st adapters in the qsys design. (You don't need to do this if there's no error or warning related to the avalon-st interface.) For the DC FIFO, I use it between two components working under different clock frequency.
Hello, YUFU0511!Do You mean, that You did not use any custom HDL blocks to connect CVI and SGDMA and You had no problems ? What SGDMA did You use - QSys component SGDMA or Wiki Modular SGDMA?