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Altera_Forum
Honored Contributor I
1,266 Views

Altera_mm_interconnect functionality

Hi All, 

I have 256 bit input data and 64 bit address in input side of mm_interconnect. In output side 256 bit data and 30 bit address. 

How this altera_mm_ interconnect transfer the data for 2 beat transfer. Will it club two 256 bit data and generate one 512 bit write data in output side or Based on byte_enable signal will it send two  

256 bit data. 

Please someone explain functionality of this.I could not find any spec pdf releated to this. 

 

 

 

Thanks 

Venkat
0 Kudos
6 Replies
Altera_Forum
Honored Contributor I
41 Views

Transfer sizes are based on the data width, not the addressing. So if your data is 256 bits on both the master and slave sides, it will take two cycles to perform two writes, barring any latency options or pipeline settings.

Altera_Forum
Honored Contributor I
41 Views

 

--- Quote Start ---  

Transfer sizes are based on the data width, not the addressing. So if your data is 256 bits on both the master and slave sides, it will take two cycles to perform two writes, barring any latency options or pipeline settings. 

--- Quote End ---  

 

 

Thanks for your reply. 

 

I mentioned wrong data width in output side.Actually input data width is 256 bit output data width is 512. So will it club two 256 data and send one packet of 512 bit for 2 beat burst transfer. 

In my simulation it is not clubbing. For every beat it is generating 512 bit data. 

 

Data - 'h55 ,'h66 (which i am sending) 

 

 

 

 

 

Beat 

Address (Input of interconnect) 

Address (output of interconnect) 

Data(Input of Interconnect) 

Data(output of Interconnect 512 bit) 

|MSB(256 bit) | LSB (256 bit)| 

 

 

64'b0000_0010_0000_0000(Base address ) 

30'h0 

256'h55 

'h | all zeros | 000000055| 

 

 

 

30'h0 

256'h66 

'h | 000066 | all zeros | 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

So the final value of address zero in slave side is 512'h 000066_00000000000000000000.. The data 55 is lost . Interconnect is generating this type of write.It is not clubbing the two 256 bit data. 

 

Is it bug in interconnect or any other mask signal is needed for this transaction(like byteenable).  

 

 

Thanks & Regards 

Muthuvenkatesh
Altera_Forum
Honored Contributor I
41 Views

I'm not sure I understand what you mean by "clubbing" the data. I presume you mean "combining." And I presume you mean the "input" side is the master" and the "output" side is the slave. 

 

For a narrower master writing to a wider slave, it will only write to the lower byte lanes unless you increase the address. Byte enables are added automatically inside the interconnect (you don't have to add them yourself).  

So your first transfer is correct. For your second transfer, you have to increase the address by 32 (256 bits / 8) to access the upper 256 bits at the slave since masters use byte addressing by default. See page 36 of the Avalon spec: 

 

https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/manual/mnl_avalon_spec.pd...
Altera_Forum
Honored Contributor I
41 Views

 

--- Quote Start ---  

I'm not sure I understand what you mean by "clubbing" the data. I presume you mean "combining." And I presume you mean the "input" side is the master" and the "output" side is the slave. 

 

For a narrower master writing to a wider slave, it will only write to the lower byte lanes unless you increase the address. Byte enables are added automatically inside the interconnect (you don't have to add them yourself).  

So your first transfer is correct. For your second transfer, you have to increase the address by 32 (256 bits / 8) to access the upper 256 bits at the slave since masters use byte addressing by default. See page 36 of the Avalon spec: 

 

https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/manual/mnl_avalon_spec.pd... 

--- Quote End ---  

 

 

Here i am doing burst transfer(burst count 2) so that i am passing only base address.Is it necessary to increase address in burst operation also in avalon ? 

 

/////////////////////////Task Which I am using ///////////////////// 

 

task automatic mm_send_cfg_write; 

input [63:0] addr; 

input bit[255:0] data[int]; 

 

`MM_BFM.set_command_address(addr); 

`MM_BFM.set_command_burst_size(2); 

`MM_BFM.set_command_burst_count(2); 

`MM_BFM.set_command_init_latency(0); 

`MM_BFM.set_command_request(REQ_WRITE); 

for(int i=0;i<2;i=i+1) 

begin  

`MM_BFM.set_command_data(data[i],i); 

`MM_BFM.set_command_byte_enable(32'hffff_ffff, i); 

end 

`MM_BFM.set_command_idle(0,0); 

`MM_BFM.set_command_timeout(0); 

`MM_BFM.push_command(); 

 

 

@(`MM_BFM.signal_write_response_complete ); 

 

`MM_BFM.pop_response(); 

 

 

endtask 

 

 

Thanks 

Venkat
Altera_Forum
Honored Contributor I
41 Views

Assuming this is a custom slave, it has to handle the bursting correctly. Only the first address is presented in a burst. Your slave has to understand where to write the second data. Again see the Avalon spec pages 31-32.

Altera_Forum
Honored Contributor I
41 Views

 

--- Quote Start ---  

Assuming this is a custom slave, it has to handle the bursting correctly. Only the first address is presented in a burst. Your slave has to understand where to write the second data. Again see the Avalon spec pages 31-32. 

--- Quote End ---  

 

 

Thanks for your guidance. 

 

As per avalon burst write/read protocol only i am giving the inputs.Stimulus part is fine. But interconnect is not combining the input data.  

My master(256bit) is narrower than slave(512bit).It should combine the two 256 bit input data and send one packet of 512 bit. 

 

 

Inside the interconnect we have one module altera_merlin_width_adapter.In that PACKING(Single bit) is one parameter for that module.Now that PACKING is zero. 

Is it related to my issue.Do you have any idea about that? 

 

Thanks  

Venkat