Hello.Our company is interested in low-latency implementation of some application-level network protocols (say, FIX or FAST financial protocols and/or some other broker firm usages of fpga, e.g. risk calculation). We're going to reseach fpga applicability to our particular needs. So we basically need to receive data from network controller (Ethernet 10G or Infiniband), perform some processing and to send it back to the network. Some parameters, needed for calculations, must be loaded from host PC while initializing the application. I need to decide which of Altera product will match to our needs, but I have no experience. i'm very sorry, but i'm also new to low-level digital curcuits (I'm a high-level languages programmer). Do I need a FPGA or SoC? I can see Ethernet ports on "FPGA" products. Do these boards contain full-featured Ethernet chips or just PHY chips and i have to implement ethernet inside fpga? I saw examples of Ethernet MAC level implementation. In this case i have to connect ethernet ip (intell. property) core to some pins of the fpga, which are connected to ethernet chip, according to the specification on particular Altera fpga? In any case i'd like to get TCP/IP out-of the box. I saw some third-party commercial IP cores at Altera site. Can they be integrated to any my fpga project (and be connected inside fpga to ethernet ip core)? On the other hand, all Altera SoC products contain HPS (ARM general purpose CPU) and some kind of OS, am i right? And there is Altera network stack implementation out of the box (not in fpga, but in software). So i can write an application in C, which runs on general purpose CPU, but when receiving network TCP packets i can pass them to FPGA, using Avalon API? And i can also interact with host computer? And which line of products suits better for this application (Cyclone/Aria, etc)? I've read about architectural deifferences between them, but didn't realize practical perfromance impact. Sorry for a lot of questions. I studied this problem the whole day, but there's to much information for person who is completely new to this area. Maybe i could get some clues for futher research. Thank you.
Hi, I will try to answer some of the questions:
Thank you. So if i want to use Altera ethernet ip core i have also to use Avalon bus core? And my business-logic core has to interact with Avalon bus core (so i need some adapter core)?Did i understang right that Soc systems have phy+mac ethernet chips? Which is an external device that is accesible to real-time OS that runs on Nios processor? >Meanwhile the Ethernet port connected to the SoC side of the chip (for boards that have them) uses Linux driver stack and are typically sufficient for most usage. I read that Soc products, based on Nios 2 processor, use MicroC/OS-II operating system, which is not Linux-based. What Linux driver stack are you talking about?
SoC products are using ARM cores, and they are located on the "Hard processor System" (HPS) part of the chip. The HPS also contains other IPs like USB controller, Ethernet MAC, and others:Cyclone V SoC: https://www.altera.com/products/soc/portfolio/cyclone-v-soc/overview.html Arria V SoC: https://www.altera.com/products/soc/portfolio/arria-v-soc/overview.html Meanwhile, you can still use Nios on the FPGA part of the device (both ARM and Nios can co-exist, you need to manage the software though).
--- Quote Start --- Thank you. So if i want to use Altera ethernet ip core i have also to use Avalon bus core? And my business-logic core has to interact with Avalon bus core (so i need some adapter core)? --- Quote End --- It depends on your implementation, it may or may not be needed. I believe you can use Nios to read back from the memory location that your IP is working on - but with Avalon adapter wrapped around you logic, you have the ability to handle back pressure and manage interrupts. This is just my thoughts - perhaps there are better explanation out there. Meanwhile, if you are using SoC and are running Linux on the ARM core, you can read/write to your FPGA IP via one of the HPS-to-FPGA bridges that uses AXI interface. Hope this helps...