Hello,In my design, I have a switch matrix that allows 12 I/O pads to be connected to 32 internal nodes depending on a configuration stored in flip-flop's. A kind of big mux that’s controlled by registers. There are about 15 derived clocks in the design. So, depending on the config, each I/O has its own input/output delay related to each clock of the design. In my “Top Failing Paths” report of TimeQuest Timing Analyzer, I get some violation (negative slack) due to timing violation from node A to node B with launch clock ClkA and latch Clock ClkA. Node A and node B are both I/O pads. This path is actually a false path if used with ClkA. I cannot set a false path between node A and node B because the others clocks in the design (e.g. ClkB) could be valid for this path. In FPGA, only one configuration is valid for the switch matrix, so I would like to analyze the timings as the registers that control the switch matrix were fixed to a certain value. On the other hand, I don’t want to optimize away by fixing theirs outputs before synthesis. Reason why, I’m looking for a “set_case_analysis” command or equivalent. Another option would be to use set false path command from node A to node B with specific launch clock and latch clock. Is it possible ? Thanks for your help.
I'm a little confused by your explanation and setup, but your last question is certainly possible (assuming rising edge triggered; falling clock edge analysis ignored with this):set_false_path -fall_from <launch_clk> -fall_to <latch_clk> -from <nodeA> -to <nodeB>
Thanks for your feedback.I'have tried your command but TimeQuest returns that : Options are mutually exclusive: -fall_from and -from. Specify only one of the two options. It's a pitty that set_case_analysis is not supported by the TimeQuest timing analyzer.