I'd like to emulating an SD card in FPGA / CPLD / microcontroller - with “data” stored over USB on host PC. After much research I think it is only possible in a FPGA / CPLD.
I'm not sure which series to look at, Terasic recommend the DE0-Nano-SoC with Cyclone V SE, but I fear that might be overkill and if I want to produce a few, the BOM would be costly. Diagram: http://www.alteraforum.com/forum/attachment.php?attachmentid=13238&stc=1 I'd like to support the max UHS-I speed SDR104 - 104 MB/s - 208 MHz. Other modes are: SDR50 - 50 MB/s - 100 MHz DDR50 - 50 MB/s - 50 MHz SDR25 - 25 MB/s - 50 MHz and slower speeds. The SD card initializes at 400 KHz 3.3v and then switches to high speed 1.8v at one of the negotiated clock rates as explained above. From http://www.alteraforum.com/forum/showthread.php?t=54852 , it sounds like the MAX 10 is capable of this, that would greatly reduce the BOM cost vs a Cyclone V SE - however I'm concerned about the clock rate at which it will run and the performance. As this is my first FPGA project, any advice you can provide on sizing would be appreciated!