Any Example on Transceiver custom phy ip with FPGA Fabric Transciever interface width of 40?

[matif1]

Can you please share any example design on transceiver custom phy ip with Transciever FPGA Fabric interface width of 40? Please dont share qsys example, I want to use transceiver without Avalon MM bus.

[CheePin_C_Intel]

Hi,

As I understand it, you are looking for an example design with Custom PHY with XCVR-Fabric width of 40. As I search through the internal database, I am unable to locate specific example design on this. However, I found a Native PHY design with 32 bits XCVR-Fabric width. It is a CV simulation example previously from wiki. I have sent it to your email for reference. 

To run the simulation, do the following:

1. Unzip the files 

2. Change the Modelsim directory to the unzipped folder 

3. Type "source simulation_setup.tcl" 

4. Type "ld" to compile 

5. Type "simulate" to start simulation 

Specific to Custom PHY, to enable 40 bits width, you can do the following settings (example only) in Custom PHY IP:

1. FPGA - XCVR width = 40

2. PCS-PMA width = 20

3. Word aligner pattern length = 20

4. Word alignment pattern = <set 20 bits pattern>

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin