Appropriate I/O standard to use DDIO for LVDS signals

[YTagu5]

Hi,

I'm using ADS5263, a high-speed ADC, and trying to receive test pattern from this ADC. To make everything simple, I first set the clock frequency of ADC to its minimum, 10MHz. Because the data is delivered with DDR, I would like to receive data using DDIO feature in GPIO IP. The ADC chip uses LVDS to deliver signal, so I set the I/O standards of pins, which are connected to ADC, to LVDS in Pin Planner.

In GPIO IP, we have an option in Buffer section: "Use differential pair". If I turn on this option, the instance of DDIO module requires input port .pad_in_b. I cannot connect negative differential signal pin to .pad_in_b, because it is already used in LVDS setting in Pin Planner.

What is the appropriate I/O standard to use DDIO for LVDS signals?

Thank you,

Yoshitaka

[Rahul_S_Intel1]

Hi,

If you using the above configuration , do you find any issues or error

[Rahul_S_Intel1]

Hi ,

 Kindly let me know, if you need further assistance.

[YTagu5]

Hi RahulS,

I'm sorry that I missed the reply notification.

At first, I was trying to use DDIO. but I found that I need phase alignment to receive data correctly, so I started to use SERDES IP. The SERDES is working properly now.

So I don't need assistance for this topic anymore.

Thank you for kindly reading my post.

Best regards,

Yoshitaka