We have a PCB board we designed with AMD 8860 GPU that sends DP video to Aria V Display Port core (Qsys). In some of our boards we sometimes have DP connection issues.
The video signal goes to altera_xcvr_native_av and when RX is out of lock we see multiple retries on the DP AUX channel.
We came across this bug:
in our case the enable GPU is not checked.
Can anyone confirm this issue is also applicable to Aria V Display Port?
What I meant on watch out on all the clock frequency that you supply to DP design is
- You have modified DP Sink IP data rate and pixel output mode setting, then I would expect you need to modify the clock frequency supplied to example design accordingly like (DP video clock, NativePHY frequency setting, IOPLL setting and etc accordingly) Else pls revert the setting back and keep the changes min
- DP aux channel carry important debug info so you shouldn't remove it. Since you mentioned it's working on your original DP design then you just need to modify the example design
- You can learn more about the DP example design in Intel DP user guide chapter 4
For MSA log dump debug :
- Below AN793 (page 20) show you screen shot of MSA log dump example
- Just wonder after you press "S" and there is no respond from NIOS II terminal ?
- Another method to trigger MSA log dump is via triggering "user_pb" signal port in DP example design
- If both method also failed then you may want to double check whether your NIOS II is initiated correctly ? From AN793 screen shot, I can see some green wording in NIOS II terminal showing connection setup to NIOS II CPU
- You can also try to reprogram the NIOS II elf file again in NIOS II command shell using below command, then repeat the MSA log dump procedure
- nios2-download dp_demo.elf
- The elf file is located in \av_sk_4k_v15_0\software\dp_demo\
I tried to download the NIOS 2 elf file and got an error (see attached).
then I checked the address of the example design Vs my modified example design and realized the address were changed during the modification process.
I think this is the root cause for NIOS load failure - I'll try to change back the address but if it will faile I'll need to create a new elf - can you please address me to suitable userguide?
by the way I'd like to verify if the AUX signal integrity is cauing the MSA drop, is there any option to redundent the AUX channel in the DP setup GUI?
Ya, you shouldn't change NIOS II address location in your design.
- If you modify the address in QSYS then you just need to change it back
- Else if you modify the c code design then you can run "build_sw.sh" script in example design to rebuild the NIOS II software and regenerate the new ELF file again.
- Whenever you touch on the design in software folder, remember to always rebuild software to generate updated elf file, then download and program ELF file again. Else you can also recompile while Quartus project to integrate ELF file design into sof file
- You can learn more about the example design in DP user guide chapter 4
Aux channel is a must for DP link training and policy maker communication update.
- Anyhow, Aux channel is just running at very low speed - 1MHz or 16MHz like that. There shouldn't be signal integrity concern but I do worry whether the Aux channel board design connection is done correctly or not.
- I found out DP board design guideline doc (AN745, page 9 onwards that talks about Aux channel design). You can want to check it out as well
It's good to know that you have AV dev kit board and Bitec DP daughter card to port over the DP example design.
Yet I noticed you are not using AV starter kit board that matched with AV example design pinout setting.
- That means you need to manually check the pin connection on your AV board and modify the example design pin setting accordingly.
From your NIOS II terminal screenshot, I can see the "Started ..." print out which means NIOS II is already running. You just need to press wither "s" button or the user_pb button to dump MSA log
- If it doesn't work and nothing happen then I suspect could be due to wrong clock frequency to NIOS or user_pb pin assignment is not done correctly
- In short, pls ensure all the DP connection, IO standard, clock frequency, reset control and user_pb setting is being taken care of to match with your AV board design
From my side, I will check next week to see if I can find AV started kit board in office to program the example design and show you screenshot of MSA dump. (I am now working from home due to Covid 19 control restriction in my country. We required permission to go back office)
Thanks for your understanding
I'm sorry - the setup photo I sent was taking from DisplayPort_RX_and_TX_Desgin_Example_AN_r1.pdf page 41#, my board is the Arria V starter KIT (see photo). I checked the pinout of a few signal in the project pin planner vs the schematics of my board and verify it matches. Then I recompile av_sk_4k project an this time I managed to get the log output (see MSA_LOG.txt) but there is no image on the TX and RX is not detected on my PC as a secondary screen.
looking on the Bitec Display Port Daughter Card schematics and A5GX_STARTER_C.pdf schematics – it looks like the HSMA_TX_P4 to HSMA_TX_P0 was cross routed (e.g 4# goes to 0#) I changed that but got the same results.
then I checked the PLL of my design example vs the above PDF and see some gaps.
according to the pdf the top module is not top.v but sv_dp_demo.v and it looks very different from the top level entity I found at altera\15.0\ip\altera\altera_dp\hw_demo\av_sk_4k. (see image SV_DP_DEMO-Top module.jpg can be found at the pdf on page 3#)
from the above PDF link - it looks like this Bitec Display Port Daughter Card was tested with a different example design.
Also I discovered that our design was based on this sv_dp_demo.v entity and not the top.v.
I managed to find this sv_dp_demo.v design example and tried to test it on the same setup but unfortunately the elf was failed to load.
I tried to migrate this project to Quartos 15.0 but the IP upgrade was failed (see attached log)
Please advise how can I proceed.
You probably miss out my earlier AV DP example design explanation.
- Pls don't refer to other DP example design link else it will create extra confusion to you.
For AV DP example design :
- You should just use the av_sk_4k example design that I shared with you
- The example design doc explanation is available in DP user guide doc chapter 4
You do not need to change anything on this example design if you are already using AV starter kit board + Bitec HMSC rev 11 DP daughter card
- Just compile original av_sk_4k design (unchanged), program the sof file. That's all. NIOS ELF file download is not required.
- Anyway, attached is the AV example design sof file for your reference again
- Make sure you use "factory default switch setting" following AV starter kit user guide doc (page 18)
Next let's discuss about your MSA log file
- May I know this MSA log file is result output from AV starter kit board or your own custom board ? I presume it's AV starter kit board result ?
- From the MSA log file, you can see that the BER rate is pretty bad for all lanes.
- If you are using AV starter kit board then byright your board signal integrity is good. It shouldn't be that bad unless there is some issue with your board or the Bitec daughter card itself
- Ensure the Bitec daughter card is tightly connect to the board and the AV starter kit board is set with all default switch setting
- Else you can also try with the sof file that I attached in previous post
- You can also change DP cable or switch to test out other GPU since you already have golden ref design and board.
- Pls try out lower video resolution as well
- Another option is to change DP IP bit per colour (bpc) setting to either 8 to 10 to try out
- Else if the MSA log is from your own custom board then you know that your board SI is pretty bad
- Then you will need to review your board SI issue accordingly
In my priveouse post I was referring to the av_sk_4k.
I programed the sof file you sent and got the same results:
LEDs in on state: D21, D22, D23, D24, D12, D15
LED D20 - is bilnking
LCD show message "Not Connected"
Cable were tested OK from my PC to the monitor, all the av sk SW setting are default and similar to page 18#.
Checked with alternative GPU and also with 800X600 resolusion and with color depth =8 bit and it still looks similar.
Bitec daughter displayport card is tightly secured to the AV SK with screws.
when I'm not loading the NIOS (as you suggested) I can't get the MSA LOG - please see attached terminal capture.
=Can I assume there is a failure in the hardware?
Please advise how can we tell if the failure is on the Arria V SK or at the Bitec daughter displayport card?
I can see that the Bitec Displayport can also be Compatibility with:
•Arria II and V
•Stratix I, IV and V
we should also have Stratix IV and I get other evaluation kits as a loan - do you have an example design sof file for all of those cards?
Transceiver architecture design is different from one FPGA family to another. So, not recommended for you to switch to other FPGA product as well.
It's preferable to stick with AV example design to debug either on your custom board or using the AV starter kit board.
For AV starter kit board debug :
- No, we don't have good way to isolate whether it is dev kit board or Bitec daughter card issue. You can check with whoever person that passed you these board to figure out whether the board is still healthy or any special board rework is done in the past or not
- Your latest NIOS II screenshot showing somehow the initialization is not completed and seems stuck.
- Have you tried to toggle the resetn pin control via pressing push button switch 4 ?
- Or reprogram NIOS II elf file again to see if it helps ?
- Other thing that you can check on the dev kit is launch the clock controller GUI software that comes with dev kit installer software to verify you are outputing the correct clock frequency to AV DP example design
For your own AV custom board debug :
- This is another debug direction also since our original debug goal is to verify your board SI issue via MSA log dump
- We wanted to bring up NIOS II to dump MSA log and you have successfully done it on AV started kit board
- Can you revisit your own board to bring up NIOS II and dump MSA log with "modified AV example design that match your board connection" ? This will be more meaningful than spent time to debug AV starter kit board
The other thing that I can think is the Quartus old known issue impact.
- Older Quartus version like v15.0 may contains some bug that got fixed in newer Quartus version
So, it's recommended for user to always upgrade to later Quartus version like for instance v18.0 or v19.1 to avoid facing old bug issue in older Quartus version.
Therefore, you can upgrade the DP example design to newer Quartus version and retest it as well
I managed to go back office today (despite bad COVID situation) to run some hardware testing and found out v15.0 example design indeed is problematic, likely due to some old known issue bug as I explained to you in my previous post.
I validated v18.0 and v20.1 Quartus Standard example design and it's working.
- I can see video output and in NIOS II terminal, just press "s" key or push button 0 then it will dump MSA log
- You won't see the all zero value in MSA log anymore
I will generate Intel SFTP server and share the v20.1 example design zip file with you. You can try out the sof file in the zip file directly on your AV starter kit board.
I download the files you shared and programmed it with Quartus 15.0. The DisplayPort input signal was created on my laptop with a USB C to DisplayPort converter. After programming the SOF file my laptop just freeze and the only way to resolve it was to disconnect the DisplayPort. So I found another computer with native DisplayPort output and finally I got dissent MSA log (see attached txt file). I also print the vesion in the attached file.
However I still get no image on the DP Tx output display.
Please advise if this looks like Hardware issue?
I'm trying to purchase a new Arria V SK but since this board was discontinued it is hard to find. we can purchase the Arria V Development kit, do you think I can use it in the same manner? how much extra work is the porting from SK to the DK?
The next step is to port our design and run it on the Arria V starter kit and check the msa log. I assume I'll need to add some Nios 2 components to our design. Hope you can support me with this action. Another idea is to output the msa failure signal and check if it fails after sometime with SignalTap or actual oscilloscope.
I wonder if the bug you found on the 15.0 design example may appear on our design as well and even may be the root case to the failure we have?
It's not recommended to move example design to different AV dev kit board as this is not something Intel validated before and we can't guarantee it will work.
For MSA log review,
- I compared both the Quartus v15 and v20.1 example design MSA log
- in v15.0 MSA log :
- everything is mess up. Link training is failing with high BER number
- in v20.1 MSA log :
- Situation is improving likely thanks to bug fixed in older Quartus version.
- DP link training is passing. (CR DONE = F, SYM DONE = F). BER number also zero now (good). Meaning DP data transfer is happening on your AV starter kit board which likely means your starter kit board is in good condition else link training will failed.
- The only issue remaining is Rx MSA active video info is all zero. This looks to me your GPU/DP source is not transferring any active video to AV starter kit board for whatever reason. You may want to back your GPU source or try different GPU source. Don't use fancy USB to DP converter as you are adding additional complexity that may caused other issue. Pls stick with direct GPU card -> DP cable -> AV starter kit board connection
Below is my debug suggestion plan
- Upgrade your custom DP design on your custom board from Quartus v15.0 to v20.1 standard
- This is to validate whether the Quartus bug fix help to resolve your original issue
- Modify v20.1 DP example design to match with your custom board
- You tried this before using v15.0 DP example design but failed. I believed it's likely due to Quartus bug in v15.0 but should be fine now with v20.1 example design
- The benefit is you can dump MSA log to validate the BER number that's questionable is the past in v15.9 design but now we have confirmed v20.1 design is output zero BER on AV starter kit board as long as the board design is good
- 3rd option is to port over your custom DP design into AV starter kit board
- This is your debug plan but my advice is you at least need to bring up a working system setup on AV starter kit board before you port over your custom DP design
- Before you do this, it's recommended to resolve the zero Rx MSA info issue first on why GPU/DP Tx is not transmitting active video to AV starter kit board
- I am using the exact v20.1 example design sof file but it works on my Intel hardware setup. GPU = Nvidia GTX 1080 and I also tried both Philip and LG monitor.
- Sometime if there is not video output on monitor, pls press cpu_resetn button on AV starter kit board to reset DP IP and restart link training again
I added a small process to the av_sk_4k_dp_demo that count how many MSA_lock toggles I have just to verify this output and also aded a signalTap to this counter. after compilation I got the below file:
I didn't have any issue programing this sof with the quartus programmer 20.1 but the signalTap Scan chain (with the eame USB Bluster) does not detect any device.
Is ther any limitation here? do you have any idea why it is not detecting the avaluation board?
This is weird.
The only 2 reason that I can think of is either
- You didn't enable the signal_tap *.stp file correctly in your quartus design
- Ensure you added signal_tap *.stp file in Quartus setting and recompile design
- You should see a lot of additional signal_tap setting in Quartus project *.qsf file if you added signal_tap and compile successfully
- Or there is something wrong with your board JTAG connection
- You can try reduce JTAG frequency from 24MHz to either 16MHz or 6MHz to see if it helps
Likewise you can also create simple one wire dummy Quartus design and add signal_tap to isolate is it DP Quartus design issue or your board issue
I managed to program the starter kit 20.1 design example with Quartus 18.2. Looks like a bug that appears sometimes.
I tried to port the design example to our board but it seems the ALMs requirements for the example design is 5% higher than our PLD resource.
29,792 / 28,300 ( 105 % ) Logic utilization (in ALMs)
Is there any way to reduce the design example a bit? We are trying to purchase a larger pld and migrate our board.