Array Problem

Altera_Forum · ‎04-20-2011

Hi again,

When i compile the following code it eats all my logic.

I'm pretty sure its a problem with the use of arrays.


 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity VERTICAL_COUNTER is
 port 
 (
  RESETn       : in std_logic;
  CLK100MHz      : in std_logic;  
 
  COUNTER_ABLE   : in std_logic := '0';
 
  CAM_FRAME_VALID   : in std_logic := '0';
  CAM_LINE_VALID   : in std_logic := '0'; 
 
  CAM_DATA_VALID   : in std_logic := '0';
  CAM_DATA    : in std_logic_vector (7 downto 0) ;
  READ_FROM_ARRAY   : in std_logic := '0';
  WRITE_ENABLE   : out std_logic  := '0';
  DATA_VALID    : out std_logic  := '0';
  DATA_OUT    : out std_logic_vector (7 downto 0); 
 
 -- ARRAY_ERROR    : out std_logic  := '0';
 -- COLUMN_NUMBER   : out std_logic_vector (10 downto 0);
 
  OUTPUT_amp_max    : out std_logic_vector (7 downto 0);
  OUTPUT_amp_06   : out std_logic_vector (7 downto 0);
  OUTPUT_amp_n1_greater : out std_logic  := '0';
  OUTPUT_position   : out std_logic_vector (7 downto 0)
 
 
 
 
 
 );
end entity;
architecture rtl of VERTICAL_COUNTER is
type array_type_8bit is array (0 to 1279) of std_logic_vector (7 downto 0); 
type array_type_1bit is array (0 to 1279) of std_logic; 
signal  array_amp_max , array_amp_06 , array_position  : array_type_8bit ; --:= (others => (others => '0'));
signal array_amp_n1_greater         : array_type_1bit ; --:= (others => '0');
 
signal counter      : integer range 0 to 1280   := 0;
signal line_counter    : integer range 0 to 255   := 0;
signal read_counter    : integer range 0 to 1280  := 0;
signal counter_max    : integer range 0 to 2047   := 0;
signal data_loaded    : std_logic := '0';
signal send_data    : std_logic := '0';
signal buff_line_valid   : std_logic := '0';
signal out_amp_max    : std_logic_vector (7 downto 0) := (others => '0');
signal out_amp_06    : std_logic_vector (7 downto 0) := (others => '0');
signal out_greather    : std_logic      := '0';
signal out_position    : std_logic_vector (7 downto 0) := (others => '0');
 
begin 
prog_adr : process (CLK100MHz) begin
if rising_edge  (CLK100MHz) then
 
 data_loaded  <= '0'; 
 counter   <= counter;
 read_counter <= read_counter;
 
 WRITE_ENABLE  <= '0';
 DATA_VALID  <= '0';
 DATA_OUT  <= (OTHERS => '0');
 if  COUNTER_ABLE = '0' then -- reset condition
  send_data   <= '0';
  counter   <= 0;
  read_counter <= 0;
 else -- COUNTER_ABLE = '1'
 
  if CAM_FRAME_VALID = '1' then -- or data_loaded = '1' then
     read_counter <= 0;
     send_data   <= '1';
 
     buff_line_valid <= CAM_LINE_VALID;
     if buff_line_valid = '1' and CAM_LINE_VALID = '0' then 
      line_counter  <= line_counter + 1;
      counter_max  <= counter;
      counter   <= 0;
     end if;
     if CAM_DATA_VALID = '1' then -- and data_loaded = '0' then
      data_loaded   <= '1';
       if CAM_DATA >= array_amp_max(counter) then    
        out_amp_max   <= CAM_DATA;
        out_amp_06   <= std_logic_vector( to_unsigned(  to_integer( unsigned(  CAM_DATA )) * 16 
                     +  to_integer( unsigned(  CAM_DATA )) * 2 
                     +  to_integer( unsigned(  CAM_DATA )) + 16 , 13))(12 downto 5) ;
       else 
 
        out_amp_max   <= array_amp_max(counter);
        out_amp_06   <= array_amp_06 (counter);   
       end if;
 
       if CAM_DATA > array_amp_06 (counter) then 
        out_greather      <= '1';
       else
        out_greather      <= '0';
       end if;
       if CAM_DATA <= array_amp_06 (counter) and array_amp_n1_greater(counter) = '1' then
        out_position    <= std_logic_vector (to_unsigned(line_counter,8));
 
       else
        out_position    <= array_position(counter);
       end if;
 
     else
 
      if data_loaded = '1' then 
 
        counter <= counter + 1;
 
        array_amp_max(counter)   <= out_amp_max;
        array_amp_06(counter)   <= out_amp_06;
        array_amp_n1_greater(counter) <= out_greather;
        array_position(counter)   <= out_position;
 
      end if;  
 
     end if;
 
  else
    counter   <= 0;
    line_counter  <= 0;
 
    if  send_data = '1' then 
 
     WRITE_ENABLE <= '1';
 
     if read_counter >= counter_max then 
      send_data <= '0';
 
     elsif READ_FROM_ARRAY = '1' then 
      read_counter  <= read_counter + 1;
      DATA_VALID  <= '1';
 
      DATA_OUT  <= array_position(read_counter);
 
      array_amp_max(read_counter)   <=  (others => '0');
 
     end if; 
    end if;
  end if;
 
 end if;
 
end if;
end process;
end rtl;

Explanation:

When frame valid (image is read in) i'm doing some actions.

1) searching the max amplitude in every column.

2) calculating MAX value * 0,6 (see an other topic i started)

3) Searching the calculated value in the column and

storing the position (line number).

When frame is not valid, i can read out the array (RAM)

My last problem with arrays was when i made the whole array empty

so it didn't used RAM but logic.

Q: Why is it making logic this time ? Anyone has a better way to write

this code? (Less resources and still readable, cauze i'm still learning)

Altera_Forum · ‎04-20-2011

I think the compiler has a problem to synthesize a Ram because of following code:

if CAM_DATA >= array_amp_max(counter) then
. . .
out_amp_max   <= array_amp_max(counter);
. . .

In these lines you are asking from the MLAB RAM to deliver a result in one clock cycle, which it can't. The Read Address is first registered before being applied to the RAM-cells, which delays the result by one clock cycle. So the compiler uses logic cells to build that section, requiring 1280 * 8 LEs per array. I suggest you read about the internal RAM blocks.

I never have the compiler infer a RAMs for me, I always either use the MegaWizard, but most often I instantiate a RAM component directly (peeking into what the MegaWizard generates helps to understand what generics to apply).

Altera_Forum · ‎04-21-2011

Thx! I'll should do some reading :)

Altera_Forum · ‎04-21-2011

With some syntax issues getting figured out, i have it working like a

charm!!( used dual ram template )

Thx josby and till my next question.