EP2C20Q240 and SDRAM problem

[Altera_Forum]

Hi all, 

 i hope this is the right section of the forum. We have been working on a control system for an industrial project (which is not in a bad shape thanks to this forum :). Right now we have built our custom board, with an EP2C20Q240, JTAG and Active serial programming interfaces, an SDRAM Micron MT48LC16M16A2 and a Flash memory (which we have not yet checked). We are able to communicate with the JTAG, program the FPGA using any of the two interfaces and we have also succeeded in setting up a simple VHDL and a simple nios core into the FPGA.   Now the bad news: we cannot use the SDRAM.  1) If we try to set a nios sytem we get the error "m_state == STATE_DEBUG" failed etc.... We can get the nios eclipse just blocked depending on the PLL tuning 2) trying to debug with the System Console (Avalon master, SDRAM and no nios) we are able to write and read but 10 % of the time we get the wrong values. Also as soon as we change something it hangs up. 3) PLL tuned to many different values without result 4) even connected a logic analyzer, but we don't know what to look for as the Avalon master is continuously operating and it does not provides the ns resolution needed for this  Sorry for the long description. Obviously it looks like a timing issue, but after a few days we don't know how to debug it in an intelligent and reasonable way (is a clock issue related to some of the lines, is some certain connection wrong, is the layout, is coupling, what the $%#@ it is...).   We would really really really thank any valuable debug roadmap or suggestion.....